I am trying to listen in on a SPI-like protocol which is transferred on one busline in both directions (no slave-select). To discriminate which data is sent by which side, I need a bus splitter that transmits the data but lets me see which side it was generated on. The bus idles on high on 5V and is pulled low by either side for clocking out bytes at 156kHz.  I found the following design  (fig. 6) and implemented it on a bread board. For R1 I used 10kΩ. The NOR-gates are  and the MOSFETs are  (I used BJTs before which resulted in too much of a voltage drop). The power source/groudn level is driven by the master device so that all voltage levels match with the other bus lines (which I do not need to split).    Going over it with a multimeter/Arduino testing program, everything seemed to work okay. When I inserted the circuit into my bus line though, the slave would not be identified by the master anymore. For debugging I set up function generator and oscilloscope and tried to simulate the square wave type signal. Curiously enough, when I applied idle high state on IN1, its voltage would be reduced to around 2.5V, the OUT2 would see sharp peaks to low (otherwise idling on high) and the IN2, where the data from IN1 should be transmitted to in an transparent manner, was a saw tooth. The same behaviour appears with the actual apparatus just idling on high, there is no signal going on here, yet there is an oscillation  IN1 is set to 5V, others floating. Ch1 (blue) is OUT1 (where there should be the inverted signal of IN1), Ch2 is IN1 (which should be steady at 5V   In this picture same setup, IN1 to 5V, others floating. Ch1 is OUT2 (which should low as it inverts the free state of IN2) and Ch2 is IN2 (which should be the signal from IN1, thus high.   Why is the device not working as advertised? I thought the description of it made sense. While looking up  on Wikipedia I noticed that the device basically is two flip-flop designs thrown together, and that flip-flops might generate these oscillations.   I also added various resistors at U1/2 or between the MOSFET and Q1/2 or between the gat of the MOSFET and GND, to no success. I generally don't have much knowledge of electronics and am just hopelessly puzzled. Does anyone recognize the mistake or can point me to another working design for this type of device?
I am trying to sniff on a custom SPI-like bus protocol, which uses a unified bidirectional data line instead of separate MISO/MOSI. To make sense of the communication, I need to split it up into unidirectional lines before feeding them to my logic analyzer. Otherwise I wouldn't be able to see which device is responsible for which part of the signal. Since my devices won't talk to each other unless the protocol is carried out correctly, it's obvious that the bus splitting device has to be transparent to the actual agents communicating.  I tried to construct a bus splitting device, but failed as described . Since this question was maybe too specific and has not been answered, I want to ask more generally: Is there a bidirectional bus splitter that is able to split  into four wire SPI? Where could I buy such a device? (This seems similar to  question, only that I'm not talking about two really different protocols, so the answer does not apply). In principle only getting one direction would also suffice, since I could just subtract it from the full signal in order to retrieve the other half. And I'm also only interested in the master side of the communication.    The  seems to be a good candidate. Although it's advertised for use with I2C, it seems to be agnostic to the actual protocol on the lines. (As it does not even differentiate between DATA and CLOCK line for I2C.)     Splits I2C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths.   As my devices operate on SPI mode 3 (polarity 1, idling on HIGH), the implementation of the receive pin should work:        sense the voltage state of the I2C-bus pin Sx (or Sy) and transmit this state to the pinTx (Ty respectively), and   sense the state of the pin Rx (Ry) and pull the I2C-bus pin LOW whenever Rx (Ry) is LOW.      But I am still puzzled on how this would actually work in sniffing this bidirectional bus. I could connect one device with the I2C line and grab its MOSI at Tx and MISO at Rx, but I would eventually have to connect both lines before feeding it to the other device, therefore making it impossible to separate the signals at my logic analyzer again. How can I connect the Tx/Rx for the slave while still being able to read them separately with a third device?  Edit: I now think this is actually not helping at all, since it leaves me with the same splitting issue as with out the device. I already have separate master and slave lines, I just don't know how to join them while still retrieving the separate directions.    I also stumbled upon the . It seems like this is a device designed for sniffing on buses, but I don't think it can help me in my case. Is there a mode where I can use it as a bridge on a bidirectional line and grab unidirectional signals off of it simultaneously?    Edit: I found this  which seems related to the issue. This does supposedly split the bidirectional line to feed it to two unidirectional isolators. The question is: Does this work for my setup? It describes the I2C lines being open-drain, whereas my lines are open-collector and also I'm not entirely sure if I could just leave out the isolator part and grab the signals from the lines or if these would have to be also hooked up to some transistor or be pulled high.
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