I understand that it is common for a UART scheme to use 8N1, meaning 1 start bit, 8 data bits, and 1 stop bit. Something like this:  0xxxxxxxx1  Where 0 is the start bit, the x's are the data, and 1 is the stop bit. In the case of multiple frames being sent back to back continuously, you'd have something like this:  0xxxxxxxx10xxxxxxxx10xxxxxxxx1  My question is: how can the receiver tell the difference between the start/stop bits and data bits? To illustrate this point, suppose that the data byte 0xAA is over and over. This would look like:  01010101010101010101010101010101010101010101010101  I made the start/stop bits bold for emphasis, but it seems to me there really is no way to distinguish these from the data bits.   Sure, if the receiver has had a solid error-free connection to the transmitter since eternity past, then I can see how this wouldn't be a problem. Or if the bytes are not sent back to back then it wouldn't be a problem. But I've worked with 8N1 circuits that were continuously transmitting bytes one after another, and I could disconnect/reconnect the wires mid-transmission and the receiver would always jump right back into receiving correctly. How is this possible?
122430
I'm experimenting with writing a software UART on my microcontroller using GPIO pins. This is to temporarily add a UART channel on a project until we get the new design implemented that uses a uC with more UART ports.  What I'm having difficulty with is correctly detecting a start bit in a serial stream. The source of the stream is external and doesn't care when my device powers up. So it's very likely that my device will power on and start seeing data bits in the middle of a byte transmission. Undoubtedly, that will cause my software UART to read erroneous values, as it won't be able to tell the difference between a start bit and any other high-to-low transition.  Is this an inevitable issue with a UART channel? Or is there some clever trick that the uC manufacturers use in their hardware UARTs?
35774
SEND + MORE = MONEY   Each letter represents a single digit number.  No two letters represent the same number. (Ex: if M=1 the no other letter in the problem can equal 1)  So far we've figured out that M=1, O=zero, and S is either 8 or 9  This is a very interesting problem, but we're a bit stuck and don't know where to go from here.
28149
• $C_n =$ this number of bit strings  • A binary string with no adjacent 0s is constructed by   Adding “1” to any string w of length $n-1$ satisfying the condition, or Adding “10” to any string v of length $n-2$ satisfying the condition   I still don't find that intuitive at all. Why adding up $C_{n-1} + C_{n-2}$ results in $C_n$? I have tried my best and asked my friends for help, but they find the formula unintuitive as well. Could anyone here come up with a clear explanation? Thanks!
113871
I was trying to understand UART fundamentals.It is understood that   It is an asynchronous communication protocol and hence the TX and RX clocks are independent of each other The data reception is guaranteed by the usage of start bit and one or more stop bits.Additionally the receiver must be aware of the data rate so as to generate suitable clock to drive the SIPO register used for  reception.   The questions here are  It is mentioned that normally a clock of 16X the bit rate is used to recover the data. So how is the conversion of bps to clock frequency possible? Please provide me some references to study the clocking mechanism employed in UART receiver.
32772
In chapter 2, the section on bitwise operators (section 2.9), I'm having trouble understanding how one of the sample methods works.  Here's the method provided:  unsigned int getbits(unsigned int x, int p, int n) {     return (x &gt;&gt; (p + 1 - n)) &amp; ~(~0 &lt;&lt; n); }   The idea is that, for the given number x, it will return the n bits starting at position p, counting from the right (with the farthest right bit being position 0). Given the following main() method:  int main(void) {     int x = 0xF994, p = 4, n = 3;     int z = getbits(x, p, n);     printf("getbits(%u (%x), %d, %d) = %u (%X)\n", x, x, p, n, z, z);      return 0; }   The output is:     getbits(63892 (f994), 4, 3) = 5 (5)   I get portions of this, but am having trouble with the "big picture," mostly because of the bits (no pun intended) that I don't understand.  The part I'm specifically having issues with is the complements piece: ~(~0 &lt;&lt; n). I think I get the first part, dealing with x; it's this part (and then the mask) that I'm struggling with -- and how it all comes together to actually retrieve those bits. (Which I've verified it is doing, both with code and checking my results using calc.exe -- thank God it has a binary view!)  Any help?
116991
I'm trying to work on UART for AVR. After setting the baud rate registers UBRRnX, I'm trying to configure the UCSRnA register.    I'm trying to set the 2nd bit, U2XO. Which is the right way to do it? UCSR0A = (1 &lt;&lt; U2X0)   or  UCSR0A = UCSR0A | (1 &lt;&lt; U2X0) (Notice the OR operator in the 2nd statement)
10930
I am trying deserialize data that come out of a LM98640 into 14 bits words:  Attached you can find a figure of the signals out of the LM98640.  (Figure 24 page 31)  I need to deserialize the signals TXOUT1 and TXOUT2:  A differential clock (TXCLK) is also output with transitions aligned with the center of the data eye. Data rates range from 80Mbps up to 640 Mbps.  (TXOUT1 and TXOUT2 changes as fast as a 640 MHz clock)  What kind of FPGA should i use to work at these rates?  Can i use flip flops to capture the data and a 14 bit wide shift register to pack this into words of 14 bits wide?  Or is it more complex at these rates? Am i going to face metastability problems since i assume a will be facing crossing time domains between the clock sampling the DATA out of the LM98640 and the clock of the FPGA.  The data deserialized is going to be provided to a NI DAQ or stored in a RAM.  What kind of xilinx FPGA should i use?  Thank you for your help
76150
byte x = -1; for(int i = 0; i &lt; 8; i++) {     x = (byte) (x &gt;&gt;&gt; 1);     System.out.println("X: " + x); }   As I understand it, java stores data in two's-complement, meaning -1 = 11111111 (according to wikipedia).    Also, from the java docs: "The bit pattern is given by the left-hand operand, and the number of positions to shift by the right-hand operand. The unsigned right shift operator ">>>" shifts a zero into the leftmost position, while the leftmost position after ">>" depends on sign extension. "  Which means that >>> would shift a 0 to the left most bit every time.  So I expect this code to be  iteration: bit representation of x  0: 11111111  1: 01111111  2: 00111111  3: 00011111  ...so on  However, my output is always X: -1, meaning (I guess) that >>> is putting the sign bit in the left most position.  So I then try >>, and same result.  What's going on?  I would expect my output to be: X: -1, x: 127, x: 63, etc.
12716
Generate a 256-bit random nonce. XOR it with a 256-bit reusable symmetric key. This is x.  We represent numbers in simple binary instead of a counting function. 0 in dec = [256 zeros] in binary, 1 = [255 zeros]1, 23092348 = [241 zeros]1011000000101110001111100, etc.  For each nth block needed for the length of the plaintext, XOR x with n and hash it with SHA-256 to form b[n].  Let p[n] be the nth 256-bit block in the plaintext and c[n] be the nth block in the ciphertext. Then c[n] := b[n] XOR p[n].  Send the unencrypted nonce along with the ciphertext.  To decrypt c[n], XOR it with b[n] to retrieve p[n].  Is this secure? If so, then why do we need AES-256?  If this is not secure, then is there any mode of operation for which SHA-256 is secure as a block cipher? Specifically, it would need to be used in cipher feedback, output feedback, or any other mode that only uses the cipher in the encryption direction.
12473
So, as an exercise to greater understand some things about cryptography, I decided to try and implement GOST 28147-89, which uses eight 4x4 S-Boxes. I can grasp the concept of putting 4 bits through the S-Box and getting four out, but how would one reverse this?  Furthermore, how would one reverse uneven S-Boxes, such as DES's 6x4 S-Box, when multiple inputs give the same output (e.g., for DES's S-Box S5, where inputs of 100011, 101110, 011101, and 010000 all give an output of 1000).
115433
I have a cheap wireless pool thermometer (AcuRite 617 ) and I'd like to intercept the temperature data at the receiver and use it with a computerized data-logging system.  Conveniently, inside the receiver is a small break-out board that is connected to the antenna and has digital "V", "G", "D", and "SH" pins:    Here is a segment of captured data from the "D" pin during a transmission (these happen once per minute). Before this segment, there is what appears to be much-higher-rate data, but I believe that might be noise -- this is the beginning of the 1.36kHz / 680Hz data.    I've googled a bit and can't find an encoding that looks quite like this, but if I were to guess what's going on, here's what I'm thinking:   the initial 4 cycles of 680 Hz are to synchronize the clocks but contain no data the 13 cycles of 1.36 kHz (2x the initial rate) that follow appear to have one of two forms: they either drop low before the midpoint of the cycle or after it -- i'd assume one form is a logical one and the other is a zero. after that, there appears to be a weird gap, but if you discount the part of the low that is part of the preceding "1", then the remaining gap is 735 µs, which is a (phase-correct!) continuation of the 680 Hz preamble.   Am I looking at this correctly? Is there a name for this encoding?  Some further notes on the break-out board:   the board is marked "RF211" and looks remarkably consistent with the MICRF211 "general purpose, 3V QwikRadio Receiver that operates at 433.92MHz" the MICRF211 data sheet has the following figure (with very little explanation), which looks tantalizingly like what i'm seeing except for the double-data-rate square wave as compared to my capture:    2016-02-14 Update: I've revisited this project and appear to be getting a clean 64-bit stream between a 4-cycle preamble and a 1-cycle "postamble", after which the display board shuts down the RF module by pulling ^SH low (top line):    According to Micrel's "33/66% PWM" scheme (which appears nowhere else on Google), that's  -_-_-_-_0000011110011000110000000000000000000000100011101000010010101010-_   So now I have to start manipulating the temperature to decode the bits. Here ("x") are the bits that seem to change without any apparent change in the display:  0000011110011000110000000000000000000000100011101000010010101010 ------------------------------------------------x----xxxx----xxx   I assume these are either least-significant bits or battery-level (which is only shown as "Low" when it drops significantly).  2016-02-15 Update: I'm taking the show on the road to give the new "Reverse Engineering" stackexchange a crack at determining meaning:
30671
While looking at SATA, PCIe, USB, SD UHS-II it struck me that they are all the same: digital serial bitstream, transmitted using differential pairs (usually 8b/10b coded), with some differences in link/protocol layers. Why so? Why did this become the standard? Why are there no widespread system communication protocols that heavily employ some advanced modulation methods for a better symbol rate? Am I missing something? This is not a question of "serial vs parallel" but a question of "digital signaling vs modulated analog"
2629
8 bits representing the number 7 look like this:  00000111   Three bits are set.     What are algorithms to determine the number of set bits in a 32-bit integer?
65453
Most of the time  and UART come together in serial communication theories. Are they both the same? From my readings I concluded UART is a hardware form of the RS-232 protocol. Am I correct?
15638
I saw a nice interview question for VHDL - build a system that receives a number and detects if it can be divided by 5 without remainder.  I tried to solve that with a state machine (I suppose they don't want you to use mod or rem) and while I did have initial success (numbers like 5, 10, 15, and numbers such as 20, 40, 80 worked), other numbers like 130, 75 and so on failed for me.  I would show my state machine but it's a complete mess (it's not a code, it's a drawing), and like I said, not even working.  Basically what I tried to do is write down in binary numbers that are divisible by 5, and build a state machine that will work for them.  I would be glad if you could show me how to solve this problem, and how to think when facing something like this.  Thank you!
58252
I am trying to understand some assembly.  The assembly as follows, I am interested in the testl line:  000319df  8b4508        movl   0x08(%ebp), %eax   000319e2  8b4004        movl   0x04(%eax), %eax   000319e5  85c0          testl  %eax, %eax   000319e7  7407          je     0x000319f0     I am trying to understand that point of testl between %eax and %eax? I think the specifics of what this code isn't important, I am just trying to understand the test with itself - wouldn't the value always be true?
93664
I am working on wireless communication system. We are using around 10 pairs of transmitter and receivers. We are using atmega16 microcontroller for encoding and decoding by USART ports.  Now we are able to transmit the data and receive the same in the receiver end, but there is a major problem, when we are finding the 2 transmitter data coming at the same time. The receiver is unable to get it due to interference.  Suppose one transmitter sends "SENDA" at the meanwhile another transmitter sends "GETTS", at that time the receiver can not receive proper data. As all the transmitters and receivers are working in same frequency, so this interference is occurring. How can I resolve this issue?