we are working on a circuit containing a 8086 and 8x(2KB) external memories (6116). the problem is that all control signals are asserted correctly, the address and data is provided but they are not written to the memory.  On StackOverflow:
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I have a project based on simulating operation of 8086 processor with memory and I/O devices using Proteus simulator.   Memory is eight 2K 6116 chips and I/O contains 2 seven-segment displays and a 4x3 keypad beside the address flip flops, logic gates for even and odd addresses and transceivers.   Also, I am interfacing memory using 74138 decoder and interfacing I/O with 8255.   The problem is that, during simulation, no value comes on address/data bus of processor, Meaning that control ports of 8086 have the values required as told in assembly code but every 20 bit address (16 bit address/data and 4 bit address A16..A19) take high Z value.   Is there anything wrong with internal memory start address (which is set to 0x00000) or assembly code?  .MODEL SMALL .STACK 64 .DATA     PORT_A EQU 60H;     PORT_B EQU 62H;     PORT_C EQU 64H;     PORT_CON EQU 66H;   .CODE  MAIN    PROC         MOV AX, @DATA;         MOV DS, AX;          ;Write arbitary values to memory         ;RAM1         MOV AL, 8H;         MOV BX, 14000H;         MOV [BX], AL;          ;RAM2         MOV AL, 7H;         MOV BX, 14800H;         MOV [BX], AL;          ;RAM3         MOV AL, 6H;         MOV BX, 15000H;         MOV [BX], AL;          ;RAM4         MOV AL, 5H;         MOV BX, 15800H;         MOV [BX], AL;          ;RAM5         MOV AL, 4H;         MOV BX, 16000H;         MOV [BX], AL;          ;RAM6         MOV AL, 3H;         MOV BX, 16800H;         MOV [BX], AL;          ;RAM7         MOV AL, 2H;         MOV BX, 17000H;         MOV [BX], AL;          ;RAM8         MOV AL, 1H;         MOV BX, 17800H;         MOV [BX], AL;           ;Load control word         MOV AL, 92H; (selection)(mode 0)(port A input)(port B input)(port C output);         OUT PORT_CON, AL;  PROG:            ;Interpret keypad         IN AL, [PORT_A]; COL:    CMP AL, 2H;         JNZ C1;         MOV BX, 2H;         JMP ROW; C1:     JG C2;         MOV BX, 3H;         JMP ROW; C2:     MOV BX, 1H;  ROW:    IN AL, [PORT_B];         CMP AL, 2H;         JNZ R1;         MOV CX, 1H;         JMP CALC; R1:     JG R2;         MOV CX, 2H;         JMP CALC; R2:     MOV CX, 0H;  CALC:   CMP CX, 0H;         JZ ENDKEY;         ADD BX, 3H;         SUB CX, 1H;         JMP CALC;          ;Calculate multiply ENDKEY: MOV DX, [BX];         MOV AL, BL;         MUL DL;          ;Display output         OUT PORT_C, AL;         JMP PROG;          MOV AH, 4CH;         INT 21H; MAIN    ENDP         END MAIN ```
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Considering I made an architecture to do some specific thing, wrote in vhdl, for example.  Can I 'burn' it in a fpga chip, forever? Or how should I do it, protecting the intelectual property knowing the fact it can be read from the serial flash memory?
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I'm trying to design PCB traces for a 27512 EPROM chip. But its pinout for the higher half of the address bus seems completely illogical to me and I cannot imagine how should I lay out my traces for it. Here's how the pinout looks like:    Other components have the data and address bus pins in order, so I need (and I would prefer) to keep it that way.  27512 has it in order, too, but only for the lower half of the address bus (A0..A7) and data bus (D0..D7); although the data bus goes around the bottom of the chip and around the ground pin (so I would need to trace it in some other direction or use a jumper wire to jump over my data bus).  But the upper half of the address bus jumps all around the chip and doesn't seem to follow any particular order: first it goes down (A8,A9), then it goes up starting from a completely different pin (A10,A11), and then jumps to the other side of the chip, then it jumps back to move up again, and then jumps to the other corner :-/  This is really weird to me, and I don't know how to make it in order again (especially to keep up with the order of the lower half of the address bus).  So my question is:  Is there any clever logic behind all this jumping around? I cannot imagine that the designers of the chip just put the pinout randomly (especially when they kept the order of two other buses well enough). I'm more likely to believe that they had some particular sophisticated PCB layout in mind when designing it. But I also cannot see the logic behind it.  I also took a look at other EPROM and SRAM chips and they all seem to have this very same pinout design, so I guess there was some rationale to keep it that way. But the PCB layout for this particular layout isn't very obvious to me. Is there any standard way to lay out the traces for these memory chips I should know of? Because without it, I would have to make a lot of jumpers on my PCB (one-sided) to restore the correct ordering of the bus lines.
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In pic below I have drawn a full adder and mentioned their delays, please help me to verify my answer.
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Maybe this is more of a perceptional problem, but it seems like microcontrollers have advanced by leaps and bounds in the last 20 years, in almost all regards, higher clock speed, more peripherals, easier debugging, 32-bit cores, etc...  It is still common to see RAM in the 10's of KB (16/32&nbsp;KB).  It doesn't seem like it could be an issue of cost or size directly. Is it an issue of complexity with the RAM controller above some threshold?  Or is it just that it isn't generally required?  Looking over a parts matrix at a popular Internet supplier, I see one  with 256&nbsp;KB for less than US$8, and then for a few dollars more you can find a few more that are ROMless, but it seems pretty sparse...  I don't exactly have a need for a microcontroller with a MB of volatile storage, but it seems like somebody might...
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Right, so we have 8-bit, 16-bit and 32-bit microcontrollers in this world at the moment. All of them are often used. How different is it to program 8-bit and 16-bit micrcontrollers? I mean, does it require different technique or skill? Lets take microchip for example. What new things does a person need to learn if they want to transition from 8-bit microcontrollers to 32-bit microcontrollers?
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I understand that there is such a thing as a disk controller which contains a buffer, but was wondering if the CPU reads directly from this buffer, or whether the data must first go to a specific location in memory, and then allow itself to be read by the CPU?  Does anyone also know what the buffer is called? And how does DMA fit into all this?
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My Microprocessor teacher of 8085 gave an assignment to set all flags ! I have written this little program to set all except Sign, Please help me out   MVI A,0FFH  ANI 01H  HLT
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I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout.  I know that trace length matching, via style and back-drilling, and signal grouping all matter.  I know that each group of 8 data bits plus two associated control lines need to be length matched.  I'm seeking a good summary of all the issues, or people's experience, especially if it covers both multi-chip modules and single point to point (one CPU and one memory chip) layout.  How critical is all this stuff for small single board CPU's?  I have read  and
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How does a modern CPU treat memory reads and writes on the hardware level? With old 8-bit architectures all memory locations are read and written to one byte at a time, but how do modern CPUs that have much wider data buses treat 8-bit memory? What would a modern CPU like an x86 or ARM based CPU do if it needs to read and write a value in memory which width is less than it's data bus width? AFAIK modern architectures read and write memory in chunks, so would it read and write several memory locations at a time then?
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This is the most interesting thing I have seen! I have built a  that sends data (D0-D7) to a DAC (ADV2175). The design worked fine and I just have a low frequency alias noise (). This noise was present on all my ground planes (This is in prototyping stage and that's not unexpected from the test PCB).  I started tracing the noise path by disconnecting wires to see when the noise is gone. Surprisingly even after disconnecting all VCC and GND connections (+ all VREF and logics gone to 0 or 1) the noise was present yet. The more unexpected behavior is when the DAC is just connected to DATA port+ CLK pin (all coming from the source FPGA, NO VCC or GND), it continues working and a sine wave is produced (but with the same noise)!!!  First I thought it may receive its VCC/GND form the logic 1/0 fed into it but if it was correct, it should not have produce 0x00 and 0xFF levels, but it makes those levels correctly (I changed 0xFF data stage to another level and a notch appeared on top of the waves. this shows it can build oxFF correctly).    This is a big challenge for my PCB design, as if this device really takes its GND from the data port, instead of the dedicated pins, I will have a hard time for designing a reliable ground plane for it (the return voltage should go back to a logic noisy environment and analog-digital ground plane isolation may be impossible).  Can anyone explain what is happening there?
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I have a device that needs a block of memory that is reserved solely for it, without the OS intervening.  Is there any way to tell BIOS or the OS that a block of memory is reserved, and it must not use it?  I am using this device on an openSUSE machine.
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Does anyone know of any good tools (I'm looking for IDEs) to write assembly on the Mac. Xcode is a little cumbersome to me.  Also, on the Intel Macs, can I use generic x86 asm?  Or is there a modified instruction set? Any information about post Intel.  Also: I know that on windows, asm can run in an emulated environment created by the OS to let the code think it's running on its own dedicated machine. Does OS X provide the same thing?
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If I write a program that tries to read memory at every possible address, and I run it on a "full" Unix, it will not be able to access all of the physical RAM.  But how does the operating system prevent it from doing so?  I am more familiar with small CPU architectures where any piece of assembly code can access everything. I don't understand how a program (the kernel) can detect such malicious operations.
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I have multiple devices with the same address, and only one I2C bus. If I don't want to/can't use an address multiplexer, will the following arrangement work? (sorry for the messy schematic)          &ndash; Schematic created using   SW1 and SW2 are microcontroller I/O, and are pulled low when we don't want to talk to the corresponding IC, and set to high impedance when we do want to talk to that IC. Can anyone see any problems with this, apart from with clock stretching? Assuming you choose diodes with a small voltage drop, like a schottky.  Edit:   Also assuming that the VIH and VIL all worked out with the diode drop and the VOH VOL.   The diodes could also go on the data lines instead, not sure if there would be any benefit/difference (maybe some I2C devices do something special when the clock goes low even if it's not their address? It's probably safer to not clock at all i.e. have the diodes on the clock lines.
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I just finished a test as part of a job interview, and one question stumped me, even using Google for reference. I'd like to see what the StackOverflow crew can do with it:  The memset_16aligned function requires a 16-byte aligned pointer passed to it, or it will crash. a) How would you allocate 1024 bytes of memory, and align it to a 16 byte boundary? b) Free the memory after the memset_16aligned has executed.  {        void *mem;    void *ptr;     // answer a) here     memset_16aligned(ptr, 0, 1024);     // answer b) here     }
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Im new in PIC world. I want to ask:  Do I need external pullup resistor for switches and encoders?  When I was using Atmel microcontrollers - I was just turning on internal pullup resistors in software.  In PIC18F25k50 datasheet I found information, that RB port pins are:  "Digital Output or Input with internal pull-up option"  So I assume that some ports may have internal pullups and I have to check datasheet. However I don't know what resistance is there and I can't find it in datasheet.  I'm asking because in many tutorials I see external pullups, so there must be some reason...