As a foreword I would like to say that I am asking this question as part of a computer science course assignment, and any responses here might be referenced in my report. I am ideally looking for hints and tips to get me on the right track rather than straight up solutions.  What I am trying to get my head around is a 2 bit magnitude comparator circuit that takes in 2 sets of inputs. For example set A would contain a0 and a1, and set B would contain b0 and b1. The only output I am interested in is A > B which means the sum of all inputs in set A is bigger than set B so a0 = 1 , a1 = 1, b0 = 1, b1 = 0 would overall output a 0 and so on.  I understand how a 1 bit comparator works :     this is the most basic circuit I came up with that takes in 2 inputs and gives out an output if A > B.  However, I have been stuck for several hours trying to increase the number of inputs. My initial plan was to somehow reuse the 1 bit comparator and reuse it 3 times but every time I end up with something that ends up with an overly complicated version of the initial 1 bit circuit where the 3 inputs actually only give out 1 output and so in the end you are going in a circle and comparing 2 numbers rather than 4.  Any advice an tips on this would be very appreciated.
122216
I have been attempting to make a digital comparator but I am struggling to get in more than one input. The idea is that I have 2 sets of 2 numbers (4 inputs total) and I want to have the output take all 4 numbers into account rather than just 2. Here is what I roughly have so far:    What I want the circuit to do is have the two inputs in the two sets treated as separately. Any ideas on how to achieve this would be very welcome.
43185
What is the difference between a differential op amp and a comparator? I know a comparator can only give me two values (the supply values).  The differential op amp amplifies the difference between the inputs...but should a comparator not do the same then? What is the specific difference?
25099
I simply can't figure out what the capacity of this circuit is.  I can do the math myself, I just need a hint how to create an equivalent circuit where it is obvious what is parallel and what is in series...
109182
Using only three 2-to-4 decoders with enable and no other additional gates, implement a 3-to-8 decoder with enable. The inputs of the resulting 3-to-8 decoder should be labeled X[2..0] for the code input and E for the enable input. the outputs should be labeled Y[7..0].  Here's my current solution. My question is, is there a better/cleaner way to do this?
13511
I was reading upon Biham and Shamir's paper and a fact has been presented over there: if $ P_1 = \bar P_2$ and I choose a key $K_1 = \bar K_2$ then in that case  $$T_1 = DES(P_1, K_1)$$ $$T_2 = DES(P_2, K_2)$$  then $T_1 = \bar T_2$ . Does this hold for only that particular combination of S-box or it will be same for any S-box combination. I mean if I change S-boxes randomly then will it still be same?  Also there is one more thing mentioned on the paper, but I am not able to get it. PFB the image.   Here output $T$ will be $\bar T_2$ only if I $P_2$ was inserted with $\bar K$. And clearly I am entering $P_1$ (which is $\bar P_2$) hence the output can never be $T_2$. Please correct.
91699
This is supposed to be a simple NAND gate. I understand how the output is 1 if one of the inputs is zero but if both inputs are 1 then the base of Q1 is supposed to be zero. This is what I don't understand. I know that Q2 and Q3 will be in cut off so the base of Q1 is floating. If that is true, how is it zero then?When A and B are open does current flow through Q2  Q3 via R1 to turn on Q1?
37306
$ab = ba$  This is, inherently, true. Some texts drop it like an axiom without any justification. But I'm a bit curious where it stems from or basically why/how it works. If anyone could enlighten me a bit further, I'd be most grateful. Peano axioms? From set theory? Help.  What bugs me with this definition is it's real world "application":  Let's say I have a power output of 5 W ( $kg\cdot m^2 \cdot s^{-3}$) and I want 30% of that power output (to have some units and natural context).  Naturally, 30% is 30 1/100 (% is the unit). For simplicity, let's express that as:  $30$%$ = 30/100 = 3/10 = 3d$ where $d = 1/10$, a simpler unit (because %W would look... Wrong?).  So 30% of power is then $5 W \cdot 3d$, and we can force it to "make sense" if we associate d with W or basically scale the unit of power by d (which is intuitively understood as being 10 times smaller then the output of 1 W) $dW$. And we want to scale these 5 units of $dW$ three times.  $5 dW \cdot 3$  But the commutative property says it is the same as scaling 3 units of $dW$ 5 times or:  $3 dW \cdot 5$  And the result is the same. This is the bit that hurts my head, the fact it is the same. I try to interpret the same as, for example 50 J of work, it's either applying 50 N over 1 m of distance or 1 N over 50 m of distance.    Down here is additional stuff I think I have (you don't have to read it if you know how to answer immediately). I don't claim it's correct, if anyone parses this information, feel free to correct me.  $m\sum\limits_{i=1}^{n}{1} = n\sum\limits_{i=1}^{m}{1}$  This is how I've been trying to break it down, as it is repeated addition. It is repeated $n$ times and multiplied by $m$, and reverse on the right side. There is $x = m - n$, so when I multiply $n$ $m$ times, each repeated addition of $n$ lacks exactly $x$ to $m$.  $mn = nm$  $x = m-n$  $m(m-x) = (m-x)m$  $m^2 - mx = m^2 - mx$  $ true $  And yes, sadly, I realise that I am using the very property I'm trying to prove ($xm$ shifted as $mx$ on the right-hand side.)  And it even calls in the distributive property of multiplication over addition which I derive (for myself, informally) from the very nature of multiplication and the way we "process" numbers:  For example, number $55$ times $2$  $55 = 5 \cdot 10^1 + 5 \cdot 10^0 = 5 \cdot 10 + 5 \cdot 1$  $(5 \cdot 10 + 5 \cdot 1) \cdot 2$  This is the basis of our positional notation which appends digits of varying orders of magnitude or units together in a way it makes "sense". Each one is b times bigger than the one to the right. Basic stuff. It is why I expressed 10 and 1 explicitly, those are what I consider units in this case.  Now, from the definition of multiplication, which is at its heart just repeated addition, it is truly the same if you add together $2$ $50$ times and then again $5$ times or "all at once" (figuratively, we are always doing the former mentally) $2$ $55$ times.  That added together gives 110, which is true.  To me, the distributive property (in case of integer multiplication) is a repercussion of the very definition of multiplication which is repeated addition (evading strict concepts). I am not certain whether this is a good way to look at it.
117146
I would like to know how to understand/analyse the circuit below. And sorry but my level in electronics is not that high and I could only tell that the opposing transistors on the left are meant to cancel any current from the input , yet I don't really understand the B stage which I think the C stage is well related to , and if I wanted to analyse the nodes around the circuit apart from (A,B,C) How can I do it ?  Is it by measuring the current on resistors/nodes?  and note that the output voltage of the circuit in node C is zero this is what it meant to be.I would appreciate any help.  Regards
70725
I'm having trouble displaying a binary number into a display. I'm not sure of how to split a number in binary into its individual numbers.  For example, if I want to display 25, I want to split this into "2" and "5" in binary.  I have 8 bits coming in and would like to split it into two 4 bit parts with the first 4 bits representing the first digit in binary and second 4 bits representing the second digit in binary.   EDIT: To clarify, I'm trying to do this using logic gates.
3952
I have 5 buttons and only one of these can be correct, all others must be false. These 5 outputs will go into 2 outputs, in between there needs to be a circuit which changes which single button out of the 5 will go down the &quot;correct&quot; output of the final 2. The 4 remaining buttons must go to the second of the final 2 outputs. Both final outputs must give out a true signal for a brief period the same as a button on its own would produce. There should also be a way of activating the circuit. Not sure if that is explained well enough so I have made a basic diagram of what I need.  The diagram shows how I need the signal to be split. However in between the buttons and the final two wires there needs to be a circuit (marked by the grey box). This circuit changes the single button connected to the left wire. The right input should start the circuit and randomise the 5 buttons. There are no limits to size, amount of materials used or method used. This question is similar to the one asking about , but I am specifically working with Redstone circuitry - the commands solutions do not apply here
48372
&ndash; Schematic created using   Will this work as a four-bit shift register? (And by extension a shift register of any size?) Each vertical PMOS / NMOS transistor pair acts as a multiplexer, and the PMOS transistor to its left amplifies the voltage back up to close to V_high. I'd be interested in hearing people's feedback on this. Right now I have only three transistors (and a resistor) per bit. Can I really get it that small a ratio, or are there reasons why I need more transistors per bit?  It's probably worth noting that I don't have master/slave here, so I can only assert (Shift) long enough to move one bit toward the right and no more.  Furthermore, I'm not trying to say that I need a resistor with 100 ohms. That appeared to be the only resistor I could use to make this schematic! What I want is a resistor that has significantly less resistance than the PMOS it's next to when it's at high impedance, but enough resistance to prevent a short circuit from V_high to ground when that transistor is conducting.  Okay, now I've changed each of the BJT's to MOSFET's, and reduced the resistance of each resistor from 100 ohms to 10 ohms. I'm still going on the assumption that (shift) will only be asserted long enough for the gate delays of M4 and M5, and then of M6, so the value of (dataIn) will only make it to M6's output, and won't move to M8 until the next time (shift) is asserted. Is this enough to get this circuit behaving like a four-bit shift register?
32837
int temp = 0x5E; // in binary 0b1011110.   Is there such a way to check if bit 3 in temp is 1 or 0 without bit shifting and masking.  Just want to know if there is some built in function for this, or am I forced to write one myself.
69069
I had a difficult time in phrasing my question. But I was wondering if there is an operation that, when repeated n times, results in the addition operator. Same way as repeating addition n times results in the multiplication operator, and repeating multiplication n times results in the exponentiation operator etc.  So $n$ times addition of a number $x$ results in $x\times n$.  And $n$ times multiplication of a number $x$ results in $x^n$  Then my question is $n$ times ...what... results into the number $x+n$.  Let's call this operator: $@$.  For example, the following would then hold:  $$a\times a=a^2$$  $$a+a=a\times 2$$  $$a@a=a+2$$  My question is, does it make any sense thinking of such an operator, is there anything known about it, can it be followed through even further like $a\sim a = a@2$?
35774
SEND + MORE = MONEY   Each letter represents a single digit number.  No two letters represent the same number. (Ex: if M=1 the no other letter in the problem can equal 1)  So far we've figured out that M=1, O=zero, and S is either 8 or 9  This is a very interesting problem, but we're a bit stuck and don't know where to go from here.
116838
Problem: Explain why this circuit does not work for Fan-In=1 and Fan-Out=3 for all logic gates(including the complex logic gate).  Firstly, I would say the Inverter Gate is fine because it does not violate the Fan-Out=3. But I don't know what the problem is in the case of Fan-In=1.  Secondly, I would say that because x is routed to the 3 inputs of the complex logic that the Fan-In=3 thus it would overload the inverter thus making the gate not work properly.  Am I right? Hope somebody can give me a lead and or help me.
2950
I've been attempting to learn C in my spare time, and other languages (C#, Java, etc.) have the same concept (and often the same operators) ...   What I'm wondering is, at a core level, what does bit-shifting (&lt;&lt;, &gt;&gt;, &gt;&gt;&gt;) do, what problems can it help solve, and what gotchas lurk around the bend? In other words, an absolute beginner's guide to bit shifting in all its goodness.
38105
Probably everyone has once come across the following "theorem" with corresponding "proof": $$\sum_{n=0}^\infty 2^n = -1$$ Proof: $\sum_{n=0}^\infty q^n = 1/(1-q)$. Insert $q=2$ to get the result.  Of course the "proof" neglects the condition on $q$ for this formula, and the sum really diverges. However I now noticed an interesting fact:  If you use two's complement to represent negative numbers on computers, $-1$ is represented by all bits set. Also, sign extending to a larger number of bits (that is, getting the same number in two's complement representation on more bits) works by copying the left-most bit (also known as sign bit) into the additional bits on the left.  Now imagine that formally you sign-extend the number $-1$ to infinitely many bits. What you get is an infinite-to-the-left string of $1$s. Which, using the normal base-2 formula $n = \sum_k b_k 2^k$ (where $b_k$ is the bit k positions from the right, i.e. $b_0$ is the rightmost bit), that infinite string of $1$s translates into exactly the sum above! So in some sense we have an independent re-derivation of that equation.  Now my question is: Is there something deeper behind this? Somehow I cannot imagine it is just coincidential.