i have a problem with this code, because in the RTL simulation, the output Cookie appears as StX. I don't know why this is happening since i don't know verilog well.   Can someone help me?   module dispenser( CLOCK, SReset,  SBCD, Cookie, valor, reciba  );   //Port declaration input CLOCK;  input SReset;  input [3:0] valor;  output reg reciba; output reg [3:0] SBCD; output reg Cookie = 0;      always @(*)         if( valor &gt;= 4'b1000)            begin             Cookie = 1;               SBCD = valor - 4'b1000;              reciba = 1;            end         else            begin             Cookie = 0;             SBCD = valor;             reciba =0 ;             end endmodule   and this is my testbench  `timescale 1 ns/ 1 ns module vendingMachine_tst();     //Parameters     parameter TCK = 20; // clock period in ns     parameter CLK_FREQ = 1000000000 / TCK; // Frequenzy in HZ     //general purpose register     reg eachvec;       //Internal wire and reg declaration      reg [3:0] TB_Un_US;     reg [3:0] TB_Dos_US;     reg [3:0] TB_Cinco_US;     reg TB_Clock;       wire [3:0] TB_SBDC;     wire TB_Cookie;       vendingMachine vM1(        .Un_US(TB_Un_US),       .Dos_US(TB_Dos_US),       .Cinco_US(TB_Cinco_US),       .SBCD(TB_SBDC),       .Cookie(TB_Cookie),       .CLOCK(TB_Clock)      );   initial                                                 begin                                                   // code that executes only once                         // insert code here --&gt; begin      TB_Clock &lt;= 0;                          // --&gt; end                                              $display("Running testbench");                        end                                                     always                                                  // optional sensitivity list                            // @(event1 or event2 or .... eventn)                      #(TCK/2) TB_Clock &lt;= ~ TB_Clock;  initial begin                                                   // code executes for every event on sensitivity list     //Caso 1: El cliente entrega justo el precio de la galleta      #0     TB_Un_US &lt;= 4'b0001;    #6000  TB_Dos_US &lt;= 4'b0010;     #60000 TB_Cinco_US &lt;= 4'b0101;   //El cliente supera el precio de la galleta   // #0   TB_Un_US &lt;= 4'b0001; //  #60   TB_Un_US &lt;= 4'b0001; //  #600  TB_Cinco_US &lt;= 4'b0101; //  #6000 TB_Dos_US &lt;= 4'b0010; // // ////El cliente no completa el precio de la galleta  // //   #0   TB_Dos_US &lt;= 4'b0010; //  #6000  TB_Un_US &lt;= 4'b0001; //  #600000 TB_Un_US &lt;= 4'b0001;       #(TCK*300000) $finish ; #(TCK*300000) $finish ;        @eachvec;                                                     // --&gt; end                                              end                                                     endmodule
121654
i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code?       //Count   module count(clk,    rst, val, coin    ); //Declaración entradas y salidas   input  clk, rst;  input  [3:0] coin;  output [3:0] val;   reg [3:0] val;    reg [3:0] nval;     always @(posedge clk, negedge rst)       if(rst == 0) val &lt;= 4'b0000;       else val &lt;= nval;      always @(val)       nval &lt;= val + coin ;   endmodule
11351
I have a testbench written for a JK flip flop. Below I have the correct circuit that passes the testbench and another circuit which passes the testbench as well. Is there something wrong with my testbench.  a) Correct JK flip flop  module jk_ff (input j, input k, input clk, output logic q);     always @ (posedge clk)        case ({j,k})           2'b00 :  q &lt;= q;           2'b01 :  q &lt;= 0;           2'b10 :  q &lt;= 1;           2'b11 :  q &lt;= ~q;        endcase  endmodule   b) Wrong JK flip flop but passes all test cases in the testbench  module jk_ff (input j, input k, input clk, output logic q);  always @(posedge clk)  case ({j,k})  2'b10 : q &lt;= ~ q ;  2'b01 : q &lt;= 0 ;  2'b11 : q &lt;= 0 ;   endcase  endmodule   c) Testbench  include "jk.sv"  module tb_jk();      // open fitness file     int passedFile;     reg j;    reg k;    reg clk;    wire q;     always #5 clk = ~clk;     jk_ff    jk0 ( .j(j),                   .k(k),                   .clk(clk),                   .q(q));     initial begin     // open file     passedFile = $fopen("passed.txt", "w");        clk = 0;       j = 0;       k = 1;        #10 if(clk == 1 &amp;&amp; j == 0 &amp;&amp; k == 1 &amp;&amp; q == 0) $fdisplay(passedFile, "%d", 1);          else $fdisplay(passedFile, "%d", 0);       #10 j = 0; k = 0;        #10 if(clk == 1 &amp;&amp; j == 0 &amp;&amp; k == 0 &amp;&amp; q == 0) $fdisplay(passedFile, "%d", 1);             else $fdisplay(passedFile, "%d", 0);       #10 j = 1; k = 0;         #10 if(clk == 1 &amp;&amp; j == 1 &amp;&amp; k == 0 &amp;&amp; q == 1) $fdisplay(passedFile, "%d", 1);              else $fdisplay(passedFile, "%d", 0);       #10 j = 1; k = 1;        #10 if(clk == 1 &amp;&amp; j == 1 &amp;&amp; k == 1 &amp;&amp; q == 0) $fdisplay(passedFile, "%d", 1);             else $fdisplay(passedFile, "%d", 0);         #10 $finish;         // close file       $fclose(passedFile);    end endmodule ```
531
I'm trying to install drivers for my Wifi on my HP All-in-one desktop. I've been told to show the output of the command "sudo lshw -C network" so here it is:  *-network description: Ethernet interface product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller vendor: Realtek Semiconductor Co., Ltd physical id: 0 bus info: pci@0000:01:00.0 logical name: enp1s0 version: 15 serial: 48:ba:4e:5c:06:5f size: 100Mbit/s capacity: 1Gbit/s width: 64 bits clock: 33MHz capabilities: pm msi pciexpress msix bus_master cap_list ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=2.3LK-NAPI duplex=full firmware=rtl8168h-2_0.0.2 02/26/15 ip=192.168.1.21 latency=0 link=yes multicast=yes port=MII speed=100Mbit/s resources: ire:31 import:e000(size=256) memory: fea04000-fea04fff memory:fea00000-fea03fff  *-network UNCLAIMED description: Network controller product: Realtek Semiconductor Co., Ltd. vendor: Realtek Semiconductor Co., Ltd. physical id: 0 bus info: pci@0000:02:00.0 version: 00 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress cap_list configuration: latency=0 resources: import:d000(size=256) memory:fe900000-fe90ffff   Output from "lspci -nnk | grep -A2 0280":  02:00.0 Network controller [0280]: Realtek Semiconductor Co., Ltd. RTL8821CE 802.11ac PCIe Wireless Network Adapter [10ec:c821] Subsystem: Hewlett-Packard Company RTL8821CE 802.11ac PCIe Wireless Network Adapter [103c:831a] 03:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. RTS5229 PCI Express Card Reader [10ec:5229] (rev 01)
31618
Given a signal wire [7:0] dummy, how can I concatenate it n times?  That is, is there a notation for the following:  {dummy, ..., dummy} // n times   ?
15638
I saw a nice interview question for VHDL - build a system that receives a number and detects if it can be divided by 5 without remainder.  I tried to solve that with a state machine (I suppose they don't want you to use mod or rem) and while I did have initial success (numbers like 5, 10, 15, and numbers such as 20, 40, 80 worked), other numbers like 130, 75 and so on failed for me.  I would show my state machine but it's a complete mess (it's not a code, it's a drawing), and like I said, not even working.  Basically what I tried to do is write down in binary numbers that are divisible by 5, and build a state machine that will work for them.  I would be glad if you could show me how to solve this problem, and how to think when facing something like this.  Thank you!
121185
I am using VTEX (visual Tex). When I run this program, it shows a error message that is    ! Undefined control sequence. \convertto #1#2-&gt;\strip@pt \dimexpr                                      #2*65536/\number \dimexpr 1#1 ?   But this program runs in LaTeX successfully.  How can I solve this error?  \documentclass{article}  \makeatletter \def\convertto#1#2{\strip@pt\dimexpr #2*65536/\number\dimexpr 1#1} \makeatother  \begin{document} \newdimen\mylength \mylength=1in \convertto{cm}{\the\mylength}cm \end{document}      Output: 2.54 cm
94589
I'm using the x86masm dialect of Assembler and register names are emphasized even when they occur inside of a label or a hexadecimal number. For example, dh is register, but 0dh is a number, yet the dh part of it is emphasized. I haven't had this problem in listings with any other languages, so I'm assuming it's a problem with the language definition. Is there simple way to redefine the language so that this doesn't happen?    \documentclass[12pt]{article} \usepackage{courier, listings}  \lstset{   language={[x86masm]Assembler},   basicstyle=\ttfamily\small,   frame=single }  \begin{document} \begin{lstlisting} cmp al, 0dh ; dh = register, 0dh = number je somewhere \end{lstlisting}  \end{document}
42265
What does this circuit do?  It looks a little bit like a flip-flop to me, but it doesn't exactly match the circuit for an SR flip-flop .  Is this just a different way to implement an SR flip-flop, or is it something else entirely?  Thanks!  Edit: To clarify, DTR and RTS in this circuit are both 3.3V level signals, not RS-232 level signals.  This circuit comes from .  (So, DTR and RTS are coming from the CP2104 USB-to-serial converter chip.)
91896
I was tasked with creating a function "transitions" that takes as input a value of type std_logic of arbitrary length. The returned value should be an integer that records the number of transitions (0 → 1, or 1 → 0) as you scan the binary bit pattern from left to right (or right to left). For example, the value 0110010011 would return 5; the value 001 would return 1.  Below is a piece of VHDL code that you can use to test your function. Add your function to the code and simulate to check that your code is giving the correct result. Show your code and the simulation results. In your simulation, display the first 100 ns, with t2, t4, t6 and t8 all shown as either signed or unsigned decimal and data displayed as binary.  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test_transitions is end test_transitions;  architecture Behavioral of test_transitions is   signal data: std_logic_vector (7 downto 0):="01111100";   signal t8, t6, t4, t2: integer; begin   tt: process   begin     wait for 10 ns;     data &lt;= data+1;   end process tt;    t8 &lt;= transitions(data);   t6 &lt;= transitions(data(5 downto 0));   t4 &lt;= transitions(data(3 downto 0));   t2 &lt;= transitions(data(1 downto 0));  end Behavioral;   Here's what I coded but keep receiving multiple syntax errors when I perform the Behavioral Check Syntax Test in the Xilinx ISE Design Suite. Any help would be greatly appreciated.  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity TransitionFunction is end TransitionFunction;  architecture Behavioral of TransitionFunction is    function transition(signal data: in std_logic) return integer is      variable count: integer;   begin     count:= 0;     for i in data'range loop       if data(i) /= data(i+1) then         count := count + 1;       end if;     end loop;     return count;   end transition;    signal data: std_logic_vector(7 downto 0):="01111100";   signal t8, t6, t4, t2: integer; begin    tt:   process   begin     wait for 10 ns;     data &lt;= data+1;   end process tt;    t8 &lt;= transitions(data);   t6 &lt;= transitions(data(5 downto 0)));   t4 &lt;= transitions(data(3 downto 0)));   t2 &lt;= transitions(data(1 downto 0)));   end Behavioral;   Error messages:
36363
Session transcript: &gt; type lookma.c int main() {   printf(&quot;%s&quot;, &quot;no stdio.h&quot;); }  &gt; cl lookma.c Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 14.00.50727.762 for 80x86 Copyright (C) Microsoft Corporation.  All rights reserved.  lookma.c Microsoft (R) Incremental Linker Version 8.00.50727.762 Copyright (C) Microsoft Corporation.  All rights reserved.  /out:lookma.exe lookma.obj  &gt; lookma no stdio.h
61828
I am using cryptocode package to make a protocol of 4 players.  \fbox{ \procedure{name}{%  \textbf{Alice}  \&lt; \textbf{Verisign}  \&lt; \textbf{Eve}  \&lt; \textbf{Bob} \\ \sendmessageright{top=\text{hello}} \&lt;\\ \&lt;\sendmessageright{top=\text{hello}} \&lt;\\ \&lt;\&lt;\sendmessageright{top=\text{hello}} \&lt;\\  }  }   I think it is very complex package with no clear documentation. I am writing to ask from experts if it is better to stick to cryptocode or to use TikZ for such diagrams.  And if any one can help me with this example using TikZ i would appreciate it :-)  thanks
6798
I'm using quartus II to design a JK Flip Flop. However, my results show unknown output. Why is it?  Intended design circuit:    VHDL code:  library IEEE;  use IEEE.STD_LOGIC_1164.ALL;  entity JKFlipFlopGate is     port(         J,K,Clk : in std_logic;             --JK Flip-Flop gate input 1 &amp; 2         Q,Qbar : out std_logic              --JK Flip-Flop gate output     ); end JKFlipFlopGate;  architecture result of JKFlipFlopGate is         signal out1,out2,out3,out4 : std_logic;  begin     out1    &lt;= NOT(J AND Clk AND out4);                      out2    &lt;= NOT(K AND Clk AND out3);      out3    &lt;= out1 NAND out4;     out4    &lt;= out2 NAND out3;      Q       &lt;= out3;     Qbar    &lt;= out4;     end result;
13950
I'm just wondering where these values are being set and what they default to? Mine is currently 18446744073692774399. I didn't set it anywhere that I can see.  $ cat /proc/sys/kernel/shmmax  18446744073692774399  $ sysctl kernel.shmmax kernel.shmmax = 18446744073692774399
89053
Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this:  node [range_hi:range_lo]x;   and others that are defined like this:  node y[range_hi:range_lo];   I understand that x is defined as packed, while y is defined as unpacked.  However, I have no idea what that means.  What is the difference between packed and unpacked vectors in System Verilog?  Edit: Responding to @Empi's answer, why should a hardware designer who's writing in SV care about the internal representation of the array?  Are there any times when I shouldn't or can't use packed signals?
91899
So I'm learning C++.  I've got my "C++ Programming Language" and "Effective C++" out and I'm running through Project Euler.  Problem 1...dunzo.  Problem 2...not so much.  I'm working in VS2008 on a Win32 Console App.  Whats the Sum of all even terms of the Fibonacci Sequence under 4 million?    It wasn't working so I cut down to a test case of 100...  Here's what I wrote...  // Problem2.cpp : Defines the entry point for the console application. //  #include "stdafx.h" using namespace std;  int _tmain(int argc, _TCHAR* argv[]) {     cout &lt;&lt; "Project Euler Problem 2:\n\n";     cout &lt;&lt; "Each new term in the Fibonacci sequence is generated by adding the previous two terms. By starting with 1 and 2, the first 10 terms will be:\n\n";     cout &lt;&lt; "1, 2, 3, 5, 8, 13, 21, 34, 55, 89, ...\n\n";     cout &lt;&lt; "Find the sum of all the even-valued terms in the sequence which do not exceed four million.\n\n";     cout &lt;&lt; "Answer:  " &lt;&lt; Solve(); }  double Solve() {     int FibIndex = 0;     double result = 0.0;     double currentFib = GenerateNthFibonacciNumber(FibIndex);     while (currentFib &lt; 100.0){         cout &lt;&lt; currentFib &lt;&lt; " " &lt;&lt; (int)currentFib &lt;&lt; " " &lt;&lt; (int)currentFib % 2 &lt;&lt; "\n";         if ((int)currentFib % 2 == 0){             result += currentFib;             cout&lt;&lt;(int)currentFib;         }         currentFib = GenerateNthFibonacciNumber(++FibIndex);     }     return result; }  double GenerateNthFibonacciNumber(const int n){     //This generates the nth Fibonacci Number using Binet's Formula     const double PHI = (1.0 + sqrt(5.0)) / 2.0;     return ((pow(PHI,n)-pow(-1.0/PHI,n)) / sqrt(5.0)); }   And here's the output...     Project Euler Problem 2:      Each new term in the Fibonacci   sequence is generated by adding the   previous two terms. By starting with 1   and 2, the first 10 terms will be:      1, 2, 3, 5, 8, 13, 21, 34, 55, 89, ...      Find the sum of all the even-valued   terms in the sequence which do not   exceed four million.      0 0 0  1 1 1  1 1 1  2 2   0 3 3 1 5 5 1 8 8 0 13   13 1 21 21 1 34 34 0 55 54   0 89 89 1 Answer:  99   So I have three columns of debug code...the number returned from the generate function, (int)generatedNumber, and (int)generatedNumber  % 2  So on the 11th term we have  55,54,0  Why does (int)55 = 54?
103238
I want to work with unsigned 8-bit variables in C++.  Either unsigned char or uint8_t do the trick as far as the arithmetic is concerned (which is expected, since AFAIK uint8_t is just an alias for unsigned char, or so the debugger presents it.  The problem is that if I print out the variables using ostream in C++ it treats it as char.  If I have:  unsigned char a = 0; unsigned char b = 0xff; cout &lt;&lt; "a is " &lt;&lt; hex &lt;&lt; a &lt;&lt;"; b is " &lt;&lt; hex &lt;&lt; b &lt;&lt; endl;   then the output is:  a is ^@; b is 377   instead of   a is 0; b is ff   I tried using uint8_t, but as I mentioned before, that's typedef'ed to unsigned char, so it does the same.  How can I print my variables correctly?  Edit: I do this in many places throughout my code.  Is there any way I can do this without casting to int each time I want to print?
17105
Suppose I declare an unpacked array of size say 8 bits wide. reg b[7:0];  If I want to assign b[7] = 1,b[6] = 1, b[5] = 1, ......b[0] = 1, then apart from assigning value to each bit is there a way to assign any combination of bits say 8'bA8, to b? For instance if I execute this code(below) in verilog: module tb();     reg [7:0]a;     reg b[7:0];     initial begin         $monitor(&quot;a = %b,b = &quot;,a);         a = 8'hA8;         b = 8'hA8; // Line 7     end endmodule  I get this error: C:\iverilog\bin&gt;iverilog -o a test.v test.v:7: error: Cannot assign to array b. Did you forget a word index? 1 error(s) during elaboration.  I am using Icarus Verilog on a command prompt on Windows 10 operating system.