According to OpenGL specs 4.5, bool in std140 layout block reserve 1 byte (sizeof(GLboolean) == 1). But when I get the offset of b, it is 4. Where is the misunderstanding?  layout (std140) uniform Uniforms {     bool a;     bool b; };   The following structure expands 4 bytes to 64. Why engineers created a so super resource-wasted standard?  layout (std140) uniform Uniforms {     bool a[4]; };
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Admittedly I don't get it. Say you have a memory with a memory word of length of 1 byte. Why can't you access a 4 byte long variable in a single memory access on an unaligned address(i.e. not divisible by 4), as it's the case with aligned addresses?
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From  it appears you would want a four-element position vector, as it is simpler to modify its position with matrix multiplication.  On its own this would imply the fourth element should simply be ignored when considering it as a representation of a 3D point (assuming no transformation), but I know this is not true, as when I supply a vector4 to the GPU, if the fourth element is not one, it is not rendered - why?  What is the significance of the fourth element, once it is in the rasterizer?   EDIT: On review this question was somewhat poorly worded; it would be more accurate for the second paragraph to say: "if the value of the fourth element is not within a certain range, it is not rendered 'correctly'/'as expected'".
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I'm currently trying to generate a really large procedural terrain in WebGL. I use a quadtree for LOD and plan to generate 1 heightmap for each quadtree node (terrain patch).  The heightmaps are generated on the GPU and with such a large terrain, 32 bits floats don't have enough precision for the smaller terrain patches. This results in terrain becoming "blocky".  uses bicubic surfaces to smooth things out.  I thought a lot about it and the only other solution I have is to generate the smallest terrain patche on the CPU (with double precision) instead of the GPU, but continue to generate the larger patches on the GPU. But this doesn't seem like the best thing to do. Does someone have an idea for a better solution?  Also, I can't use double precision on the GPU because I'm using WebGL, which doesn't support it.  Thanks a lot :)
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I am about to make a pcb footprint for this package:   But I am not sure what the two numbers mean, for example at pin 5 that 0,30/0,15. Are these maximum/minimum values in milimeters? Is that possible they have this huge difference between them?
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I am looking for details of the VTable structure, order and contents, and the location of the vtable pointers within objects.   Ideally, this will cover single inheritance, multiple inheritance, and virtual inheritance.  References to external documentation would also be appreciated  Documentation of GCC 4.0x class layout is  and the Itanium, and more broadly GNU, ABI layout documents are .
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I have a multi-threaded C++ app which does 3D rendering with the OpenSceneGraph library. I'm planning to kick off OSG's render loop as a separate thread using boost::threads, passing a data structure containing shared state in to the thread. I'm trying to avoid anything too heavyweight (like mutexes) for synchronization, as the render loop needs to be pretty tight, and OSG itself tries to avoid having to ever lock. Most of the shared state is set before the thread is started, and never changed. I do have some data that does need to be changed, which I am planning to double-buffer. However, I have a simple boolean for signaling the thread to suspend rendering, and later resume rendering, and another to kill it. In both cases the app thread sets the bool, and the render thread only reads it. Do I need to synchronize access to these bools? As far as I can tell, the worse thing that could happen is the the render loop continues on for an extra frame before suspending or quitting.
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I was writing a program in C++ to find all solutions of ab = c, where a, b and c together use all the digits 0-9 exactly once. The program looped over values of a and b, and it ran a digit-counting routine each time on a, b and ab to check if the digits condition was satisfied.  However, spurious solutions can be generated when ab overflows the integer limit. I ended up checking for this using code like:  unsigned long b, c, c_test; ... c_test=c*b;         // Possible overflow if (c_test/b != c) {/* There has been an overflow*/} else c=c_test;      // No overflow   Is there a better way of testing for overflow? I know that some chips have an internal flag that is set when overflow occurs, but I've never seen it accessed through C or C++.    Beware that signed int overflow is undefined behaviour in C and C++, and thus you have to detect it without actually causing it. For signed int overflow before addition, see .
20107
Not sure how to make tables, but:  For a binary operation $*$, and set $\{e,a,b,c\}$, in the Cayley table, $a*a$ can be filled with either the identity or an element different from both $e$ and $a$. If in the table the place for $a*a$ is filled with $e$, then the rest of the table can be filled out in two different ways.  What are the two different ways?  Thanks
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I'm building a Core  system which supports dual-channel memory (up to 16&nbsp;GB in four DIMMs), my target is 8&nbsp;GB. From the performance perspective, is it better to have two times 4&nbsp;GB or four times 2&nbsp;GB?
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The language being L, which is described as follows:  $L$ = { $&lt;M&gt;$ | $M$ accepts the binary encodings of at least 4 odd numbers } .  My solution:  M generates the binary encodings in $\Sigma_M*$ in ascending order and uses dovetailing to interleave the computation of M on those binary encodings. As soon as four computations accept, M halts and accepts.  Is this correct? What corrections would have to be made if not? I am not sure if I am providing enough details in my solution which may cause it to be incorrect.
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I'm curious why PCBs have one square pad in row for 0.1" headers. What is purpose of putting one square pad? What it indicates? Can you push more amps through square pad than round?
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I've noticed that when I do a:  ls -ls file   It provides block count, say 8 blocks.  When I do:  stat file   I notice that the block count is 16, twice the number given by ls.   The block size on my file system is 4096. I learned that the arbitrary unit for blocks used by ls is 1024. Is it correct to say that stat uses an arbitrary unit of 512 bytes when reporting blocks?  If so, is there a reason for the inconsistency?  I'm running Ubuntu 11.10 on an ext4 file system.
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I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout.  I know that trace length matching, via style and back-drilling, and signal grouping all matter.  I know that each group of 8 data bits plus two associated control lines need to be length matched.  I'm seeking a good summary of all the issues, or people's experience, especially if it covers both multi-chip modules and single point to point (one CPU and one memory chip) layout.  How critical is all this stuff for small single board CPU's?  I have read  and
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A few weeks back I was using std::ifstream to read in some files and it was failing immediately on open because the file was larger than 4GB. At the time I couldnt find a decent answer as to why it was limited to 32 bit files sizes, so I wrote my own using native OS API.  So, my question then: Is there a way to handle files greater than 4GB in size using std::ifstream/std::ostream (IE: standard c++)  EDIT: Using the STL implementation from the VC 9 compiler (Visual Studio 2008).  EDIT2: Surely there has to be standard way to support file sizes larger than 4GB.
13227
I'm trying to design PCB traces for a 27512 EPROM chip. But its pinout for the higher half of the address bus seems completely illogical to me and I cannot imagine how should I lay out my traces for it. Here's how the pinout looks like:    Other components have the data and address bus pins in order, so I need (and I would prefer) to keep it that way.  27512 has it in order, too, but only for the lower half of the address bus (A0..A7) and data bus (D0..D7); although the data bus goes around the bottom of the chip and around the ground pin (so I would need to trace it in some other direction or use a jumper wire to jump over my data bus).  But the upper half of the address bus jumps all around the chip and doesn't seem to follow any particular order: first it goes down (A8,A9), then it goes up starting from a completely different pin (A10,A11), and then jumps to the other side of the chip, then it jumps back to move up again, and then jumps to the other corner :-/  This is really weird to me, and I don't know how to make it in order again (especially to keep up with the order of the lower half of the address bus).  So my question is:  Is there any clever logic behind all this jumping around? I cannot imagine that the designers of the chip just put the pinout randomly (especially when they kept the order of two other buses well enough). I'm more likely to believe that they had some particular sophisticated PCB layout in mind when designing it. But I also cannot see the logic behind it.  I also took a look at other EPROM and SRAM chips and they all seem to have this very same pinout design, so I guess there was some rationale to keep it that way. But the PCB layout for this particular layout isn't very obvious to me. Is there any standard way to lay out the traces for these memory chips I should know of? Because without it, I would have to make a lot of jumpers on my PCB (one-sided) to restore the correct ordering of the bus lines.
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Up until now, I implemented all-against-all collision detection in my games. It worked fine.  But I reached a point where implementing this kind of collision detection, makes the game run poorly, because there are two many objects to iterate through and check for collision.  I have searched this site and found something about 'uniform grids'. But I didn't completely understand what it is and how to implement it. Tried to Google it but nothing easy enough to understand came up.  I am a beginner to 2D-game programming. Do you mind trying to explain to uniform-grids, or link me to some good tutorial?  Thanks a lot
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As you can see in object mode there are 4 vertices that have separated the front of the cartridge into multiple faces when I use boolean modifiers on cartridge.001. How can I fix this?  I imagine it has to do with good topology.  Here's the cartridge in object mode showing faces:    Here is the cartridge with the unwanted vertices:    Attached is the .blend