I'm angling this as a general question on the assumption that it doesn't differ significantly with architecture - at least at the level I'm asking.  I'm curious how - in terms of hardware, not the obvious 'result is zero' - the zero flag/status bit is set (or cleared for that matter).  It never really occurred to me before, but it seems a fairly intensive task, at least relative to say, a carry or overflow flag. Am I correct in thinking there's no way to know the result is zero, other than to check each bit?  Unless I'm missing something obvious, it seems that it must take 'a lot' (if that's sensible to say in \$\text{ns}\$) longer than determining the overflow, and the carry status of course is 'already there' as a consequence of the operation.  My question, really, is just how is it 'usually' implemented?
121122
I was implementing the ALU from the specs given in my The Elements of Computing systems book. I am stuck on only one problem. How do I find if a given number is zero or not. One thing I can do is or every bit in the bus, and then apply a not gate on that. But there has to be some other elegant solution.
58252
I am trying to understand some assembly.  The assembly as follows, I am interested in the testl line:  000319df  8b4508        movl   0x08(%ebp), %eax   000319e2  8b4004        movl   0x04(%eax), %eax   000319e5  85c0          testl  %eax, %eax   000319e7  7407          je     0x000319f0     I am trying to understand that point of testl between %eax and %eax? I think the specifics of what this code isn't important, I am just trying to understand the test with itself - wouldn't the value always be true?
76150
byte x = -1; for(int i = 0; i &lt; 8; i++) {     x = (byte) (x &gt;&gt;&gt; 1);     System.out.println("X: " + x); }   As I understand it, java stores data in two's-complement, meaning -1 = 11111111 (according to wikipedia).    Also, from the java docs: "The bit pattern is given by the left-hand operand, and the number of positions to shift by the right-hand operand. The unsigned right shift operator ">>>" shifts a zero into the leftmost position, while the leftmost position after ">>" depends on sign extension. "  Which means that >>> would shift a 0 to the left most bit every time.  So I expect this code to be  iteration: bit representation of x  0: 11111111  1: 01111111  2: 00111111  3: 00011111  ...so on  However, my output is always X: -1, meaning (I guess) that >>> is putting the sign bit in the left most position.  So I then try >>, and same result.  What's going on?  I would expect my output to be: X: -1, x: 127, x: 63, etc.
84232
Alright, I think we all agree that what happens with the following code is undefined, depending on what is passed,  void deleteForMe(int* pointer) {      delete[] pointer; }   The pointer could be all sorts of different things, and so performing an unconditional delete[] on it is undefined. However, let's assume that we are indeed passing an array pointer,  int main() {      int* arr = new int[5];      deleteForMe(arr);      return 0; }   My question is, in this case where the pointer is an array, who is it that knows this? I mean, from the language/compiler's point of view, it has no idea whether or not arr is an array pointer versus a pointer to a single int. Heck, it doesn't even know whether arr was dynamically created. Yet, if I do the following instead,  int main() {      int* num = new int(1);      deleteForMe(num);      return 0; }   The OS is smart enough to only delete one int and not go on some type of 'killing spree' by deleting the rest of the memory beyond that point (contrast that with strlen and a non-\0-terminated string -- it will keep going until it hits 0).  So whose job is it to remember these things? Does the OS keep some type of record in the background? (I mean, I realise that I started this post by saying that what happens is undefined, but the fact is, the 'killing spree' scenario doesn't happen, so therefore in the practical world someone is remembering.)
120441
I have a project based on simulating operation of 8086 processor with memory and I/O devices using Proteus simulator.   Memory is eight 2K 6116 chips and I/O contains 2 seven-segment displays and a 4x3 keypad beside the address flip flops, logic gates for even and odd addresses and transceivers.   Also, I am interfacing memory using 74138 decoder and interfacing I/O with 8255.   The problem is that, during simulation, no value comes on address/data bus of processor, Meaning that control ports of 8086 have the values required as told in assembly code but every 20 bit address (16 bit address/data and 4 bit address A16..A19) take high Z value.   Is there anything wrong with internal memory start address (which is set to 0x00000) or assembly code?  .MODEL SMALL .STACK 64 .DATA     PORT_A EQU 60H;     PORT_B EQU 62H;     PORT_C EQU 64H;     PORT_CON EQU 66H;   .CODE  MAIN    PROC         MOV AX, @DATA;         MOV DS, AX;          ;Write arbitary values to memory         ;RAM1         MOV AL, 8H;         MOV BX, 14000H;         MOV [BX], AL;          ;RAM2         MOV AL, 7H;         MOV BX, 14800H;         MOV [BX], AL;          ;RAM3         MOV AL, 6H;         MOV BX, 15000H;         MOV [BX], AL;          ;RAM4         MOV AL, 5H;         MOV BX, 15800H;         MOV [BX], AL;          ;RAM5         MOV AL, 4H;         MOV BX, 16000H;         MOV [BX], AL;          ;RAM6         MOV AL, 3H;         MOV BX, 16800H;         MOV [BX], AL;          ;RAM7         MOV AL, 2H;         MOV BX, 17000H;         MOV [BX], AL;          ;RAM8         MOV AL, 1H;         MOV BX, 17800H;         MOV [BX], AL;           ;Load control word         MOV AL, 92H; (selection)(mode 0)(port A input)(port B input)(port C output);         OUT PORT_CON, AL;  PROG:            ;Interpret keypad         IN AL, [PORT_A]; COL:    CMP AL, 2H;         JNZ C1;         MOV BX, 2H;         JMP ROW; C1:     JG C2;         MOV BX, 3H;         JMP ROW; C2:     MOV BX, 1H;  ROW:    IN AL, [PORT_B];         CMP AL, 2H;         JNZ R1;         MOV CX, 1H;         JMP CALC; R1:     JG R2;         MOV CX, 2H;         JMP CALC; R2:     MOV CX, 0H;  CALC:   CMP CX, 0H;         JZ ENDKEY;         ADD BX, 3H;         SUB CX, 1H;         JMP CALC;          ;Calculate multiply ENDKEY: MOV DX, [BX];         MOV AL, BL;         MUL DL;          ;Display output         OUT PORT_C, AL;         JMP PROG;          MOV AH, 4CH;         INT 21H; MAIN    ENDP         END MAIN ```
77308
in Rijndael SubBytes() step all bytes of input block are substituted based on a lookup table S-Box. S-Box is initialized by taking all elements of $GF(2^8)$, calculating their multiplicative inverse and then calculating their affine transform. Here is C code which does that as found on wikipedia page. #include &lt;stdint.h&gt;  #define ROTL8(x,shift) ((uint8_t) ((x) &lt;&lt; (shift)) | ((x) &gt;&gt; (8 - (shift))))  void initialize_aes_sbox(uint8_t sbox[256]) {     uint8_t p = 1, q = 1;          /* loop invariant: p * q == 1 in the Galois field */     do {         /* multiply p by 3 */         p = p ^ (p &lt;&lt; 1) ^ (p &amp; 0x80 ? 0x1B : 0);          /* divide q by 3 (equals multiplication by 0xf6) */         q ^= q &lt;&lt; 1;         q ^= q &lt;&lt; 2;         q ^= q &lt;&lt; 4;         q ^= q &amp; 0x80 ? 0x09 : 0;          /* compute the affine transformation */         uint8_t xformed = q ^ ROTL8(q, 1) ^ ROTL8(q, 2) ^ ROTL8(q, 3) ^ ROTL8(q, 4);          sbox[p] = xformed ^ 0x63;     } while (p != 1);      /* 0 is a special case since it has no inverse */     sbox[0] = 0x63; }  I cant wrap my head around how multiplicative inverse is being calculated here. I assume p here acts as input while q is its inverse. Hence $p*q = 1$. I want to understand how exactly this works because I am trying to implement a function that initializes Rijndael inverse S-Box, where first the inverse affine transform is calculated and then the multiplicative inverse.
73127
I had some intermittent trouble with the internal EEPROM of a dsPIC. Every so often, some value in the EEPROM would be found zeroed out on power-on. I tracked the problem down to when the chip lost power after the erase step of the write cycle, but before the write had completed. It was all about the timing of the power-down relative to the firmware execution, which was (in normal operation) random. I solved this by adding a buffer section to my EEPROM, to ensure that an incomplete write-cycle could be completed on restoration of power. I had to turn EEPROM writes into an atomic operation.  Now I'm using a different dsPIC without internal EEPROM, and I'm trying to use an  to store persistent data. I'm wondering if I should have similar concerns. Should I be worried that my external flash chip will power down mid-write and lose data, and write a fix for this in my firmware like I did for internal EEPROM? Or does the chip itself guarantee atomic write operations?  For further detail, my buffering technique defines an area of persistent memory that consists of three fields: address to write to, data to be written, and a READY flag. A "write" consists of four steps: write to buffer, set READY flag, write from buffer, clear READY flag. On power-up, you check the READY flag. If it's set, execute whatever's in the buffer. This worked well in EEPROM, but I'm not sure if it will work well in flash.
55096
Ok, I've always, for some reason, thought that my cpu had 32 bit registers... so I always installed the 32bit version of all OSs that I've used. Now though I ran a lscpu, and I get:  fer@fer-lap:~$ lscpu Arquitectura:          i686 CPU op-mode(s):        32-bit, 64-bit   Does this mean I can use 64 bit OSs?  Running these I get:  fer@fer-lap:~$ grep flags /proc/cpuinfo  flags       : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm dtherm   And I have read that the lm flag means long mode, which stands for 64 bit cpus. Also, as a last test, running lshw gives, for the cpu section:   *-cpu:0               descripción: CPU               producto: Intel(R) Core(TM)2 Duo CPU     T5800  @ 2.00GHz               fabricante: Intel Corp.               id físico: 4               información del bus: cpu@0               versión: 6.15.13               serie: 0000-06FD-0000-0000-0000-0000               ranura: U2E1               tamaño: 2GHz               capacidad: 4096MHz               anchura: 64 bits   It's in spanish and the last line stands for width (I guess register width). So... can I install the 64 bit of the OS? Will it be a big diference in performance? Because that's what I'm looking for (doesn't need to be a BIG difference)  Thanks in advance.
33306
Hey! I was looking at this code at   I noticed that in some situations they used hex numbers, like in line 134:  for (j = 1; val &amp;&amp; j &lt;= 0x80; j &lt;&lt;= 1, q++)   Now why would they use the 0x80? I am not that good with hex but I found an online hex to decimal and it gave me 128 for 0x80.  Also before line 134, on line 114 they have this:  small_n = (n &amp; 0xffff0000) == 0;   The hex to decimal gave me 4294901760 for that hex number. So here in this line they are making a bit AND and comparing the result to 0??  Why not just use the number? Can anyone please explain and please do give examples of other situations.  Also I have seen large lines of code where it's just hex numbers and never really understood why :(
20807
I have heard about a buffer overflow and I would like to know how to cause one.  Can someone show me a small buffer overflow example? New(And what they are used for?)
32016
I am stuck on a few issues in . (Note: It is at the frame concerning this question.)  In it, from what I understand (which could be wrong) we first apply the Hadamard gate to a qbit in the $\lvert 0 \rangle$ state. Then on that we use a controlled not on the output value, together with another input from another qbit set at $\lvert 0 \rangle$. I don't understand how to work this out and how the $\lvert 00 \rangle + \lvert 10 \rangle$ is derived for the output of combination of the two gates.  Here is what I am thinking (neglecting the $1/\sqrt{2}$ multiplier):  $$ \begin{pmatrix} 1 &amp; 1 \\ 1 &amp; -1 \end{pmatrix} \begin{pmatrix} 1 \\ 0 \end{pmatrix} = \begin{pmatrix} 1 \\ 1 \end{pmatrix} = \begin{pmatrix} 1 \\ 0 \end{pmatrix} + \begin{pmatrix} 0 \\ 1 \end{pmatrix} = \lvert 0 \rangle + \lvert 1 \rangle. $$  There however is another $\lvert 0 \rangle$ coming in from the second (bottom) wire and it interacts with the output from the Hadamard gate. I don't understand how to manipulate the values - have no idea if I can do something such as the following by distribution: $$ (\lvert 0 \rangle + \lvert 1 \rangle) \lvert 0 \rangle = \lvert 0 \rangle \lvert 0 \rangle + \lvert 1 \rangle \lvert 0\rangle. $$  I have no idea why we can do this (if we can even do so), but this is the only way I can see that we could get $\lvert 0 \rangle \lvert 0 \rangle + \lvert 1\rangle \lvert 0 \rangle = \lvert 00 \rangle + \lvert 10 \rangle$, as the author of the video has on the particular time in the video.  Any clarification would be extremely appreciated.
99037
I see this from time to time and want to know what it is. I did try google, but its filtering out the characters from the search. I have a few books that don't reference it either.   FWIW, I remember in pascal that is was the assignment operator.   Can anybody point me to the MSDN or similar page?
55119
My ever-growing interest in computers is making me ask deeper questions, that we don't seem to have to ask anymore. Our computers, at boot, as far as I understand it, are in , in which a character can be displayed using the software interrupt  when . We've all seen the famous booting font that always looks the same, regardless of what computer is booting.  So, how on earth do computers output graphics at the lowest level, say, below the OS? And also, surely graphics aren't outputted a pixel at a time using software interrupts, as that sounds very slow?  Is there a standard that defines basic outputting of vertices, polygons, fonts, etc. (below OpenGL for example, which OpenGL might use)? What makes me ask is why OS' can often be fine without official drivers installed; how do they do that?  Apologies if my assumptions are incorrect. I would be very grateful for elaboration on these topics!
60196
I have recently been looking at the datasheets for the  IC in order to see if it was suitable for my project, and have come across the following logic diagram which strikes me as a little bit odd:         &ndash; Schematic created using   For each of the inputs Yn, there are two NOT gates after the triple-input NAND gate; I don't understand why this is necessary as simple boolean logic tells us:  $$\overline{\overline{A}}\equiv A\qquad \forall A \in \{\text{TRUE}, \text{FALSE}\}$$  Therefore I am assuming there is some electronic based reason why there are two inverters before the output? I have heard not gates called Inverting buffers before, and these supposedly isolate the circuit before and after, however, I cannot claim to understand the use of this so I'd appreciate any enlightenment!
91699
This is supposed to be a simple NAND gate. I understand how the output is 1 if one of the inputs is zero but if both inputs are 1 then the base of Q1 is supposed to be zero. This is what I don't understand. I know that Q2 and Q3 will be in cut off so the base of Q1 is floating. If that is true, how is it zero then?When A and B are open does current flow through Q2  Q3 via R1 to turn on Q1?
7945
What is the difference between &gt;&gt; and &gt;&gt;&gt; in verilog/system verilog? I know that == tests for only 1 and 0, while === tests for 1, 0, X, Z. So how is that similar to the shift operator?
21752
I'm a beginner C programmer, and I assumed that this would be the case, but would like some affirmation if possible.  If they are the same, why not just take one argument instead?