I am wondering are there any standards for the order of signals on I2C header? We get many I2C devices on the market, but the order of pins on the headers is inconsistent and hence we may not be able to insert any I2C device to our board. For example, some devices have VCC GND SCL SDA, some of them have GND VCC SDA SCL and like this there are many combinations. I understand that I2C is typically used  within the board itself and hence order may not be defined. But the order of pins would matter for external devices that may be soldered directly to the header.
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EDIT: This has been repeated several times, so putting it on top: Yes, it is well known that there is no "standard" for I2C inter-device connectors, but surely this community can formulate a list of "guidance" points for making such interconnects, based on signal behavior, noise minimization, and mitigation of risk due to wrong connections.    NXP defined the  without specifying a pin-out for I2C connectors, is my understanding. The only guidance from NXP seems to be a mention of placing a Ground and / or Vss between SDA and SCL if Vss / Gnd are carried across the interconnect.  Purchases of various I2C modules has left me with a variety of I2C pin-outs, and a bit of a task keeping track of the various little ribbon-cable-switching shims I've had to make for them.   e.g.    Mono OLED module: SCL, SDA, GND, 5V (obviously not ideal, since clock and data are next to each other. Sensor Shield for Arduino: SDA, SCL, GND, 5V (again not ideal, plus switched SCL/SDA) Color LCD module: SCL, GND, 5V, SDA (Yay!) No-name I2C repeater: SCL, 5V, GND, SDA (ouch, they switched power pins! Nearly let the magic smoke out.)   So my question is this: Is there a definitive / authoritative guideline for the I2C 4-pin connector pin-out sequence to use, where both Vss and GND are to be carried from host to device?  Failing this, is there any directory, however incomplete, of I2C modules / devices listing the pin-out each has adopted?  Clarification: Looking for guidelines such as "put Vss closer to SCL because..." rather than a defined standard which clearly does not exist.
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I am trying to route a pic32 chip to a  chip and having a bit of a hard time getting all 17 address lines and all 8 data lines connected. I am trying to tie the first 16 address pins to portB pins 0-15 and the data pins to portD 0-7.  After thinking about it for a while I realized that I am probably making my life more difficult by trying to line up rb0 with a0, rb1 with a1, etc. All I really want to be able to do is write a 16 bit value to portB and have the majority of the address loaded and ready. If I make pin assignments based on ease of routing, the logical address will be different between the mcu and the ram, but it should at least be consistent. Since nothing else needs to communicate with the RAM, I don't think it will be a problem if the mcu asks for address 0x101 and the RAM gives it address 0x110.   However, I wonder if it is a good idea. If there is some structure internal to the RAM designed to make sequential reads more efficient, or something like that, then I may want to go to the trouble of routing them 1:1. The pins arrangement on both chips fees somewhat random to me, so it would make it a lot easier on me if I could ignore the particular numbers. Is there any good reason why I should or should not do that?
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Can someone help me figure out what the little letters and numbers mean on the pins of this ic?   They're used throughout various ics in this iPhone 6 schematic. Are they indicating sequence?   For example A1 happens first then A2 etc or?   Sorry that it's showing up blurry. It's crystal clear on my phone. Not sure why it's compressed like that
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I am using , which is and Bias controller/sequencer. I am using this for Providing gate voltage and drain voltage to the . In the datasheet, it is mentioned that the module with combination of EVM can be used in two applications. Application Option 1: Fixed negative gate biasing with pulsed drain biasing. Application Option 2: Pulsed negative gate biasing with pulsed drain biasing. I am trying to design both applications on a single board. The second option for future use. For the 1st application option, he has mentioned a few pins as No connection and he has used those NC pins on the 2nd application.  The issue I am facing:- They have used voltage followers for providing a low impedance output path for pin number 3(GCO). I have reverse-engineered the Ckt from the below-attached image, but I am unable to identify the voltage follower they have used. Pin number 2 of the voltage follower has been connected to pin number 2 (NC/GCP) of the Module. There has been no description of this pin number. I am guessing these:-  Pin numbers 1 and 4 are connected together and output is provided through them. Pin number 5 is +Ve supply hence connected to GND(Highest +Ve supply)? Pin number 3 is connected to -8V Pin number 2 is connected to pin number 2 of MABC-001000-DP000L, which I am unable to understand.  I have mailed component manufacturer regarding full schematic, till now I haven't heard from them. Can anybody help me with this? Thanks in Advance. Low-resolution pic of EVM. I don't think it helps in any way.   Layout Image
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I'm quite blank when it comes to electronics, but am trying to learn...   So I bought a  from Banggood to get some solder practice.   As you can see from , the leds will change color and turn on and off in different patterns.    question already establish that two pin RGB leds most likely contains some kind of micro chip, but it doesn't say anything about how they can be controlled.  The chip on the board is a STC15F204AE, and I guess that's the one responsible for creating the patterns. But again - how?  Is it just a fixed sequence pattern in the LED, and then the chip ensures that each LED receives power right after the previous, or is the LEDs addressable some how?
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Most of the interface devices have various flag bits (that can also raise interrupts if that functionality is provided) used to check the status of the device/operation.  Usually they are cleared by writing a '1' to said bit.  Just some questions regarding this ...   Why are they cleared by writing a 1? I mean if the flag is already set to 1 by the device, won't it make sense to clear it by writing a 0 to it? Lets say i have a 8 bit status register with bits distributed as (picked from datasheet of NRF24L01+)     If bit 5 (TX_DS) gets set (ie. turns to 1) and I want to clear it by writing 1 to it, what value do I write to the register.
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of the 24LC256 EEPROM states that:     The SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz).   I thought that any resistor with a kΩ value would do the job (and it seems that my EEPROM works fine at different frequencies with a 10 kΩ resistor).  My questions are:   is there a correct value for pull-up resistors ? is there a law/rule to determine this value ? how do different resistance values affect the I²C data bus ?
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This is related to another question I've just posted (), regarding the battery charger described in the , which one day I hope to build.  On page 40, there's a schematic showing the MCU connections (picture below). Marked in red is a 0&Omega; resistor that is puzzling me. I suspect that it is just a wire jumper linking AGND and GND. But I don't understand why there's a jumper there.     My questions:    What does the jumper represent? Why are AGND and GND separated like that?
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Lots of chips nowadays require smoothing capacitors between VCC and GND for proper function. Given that my projects run at all sorts of different voltage and current levels, I was wondering if anyone had any rules of thumb for a) how many and b) what size capacitors should be used to ensure that power supply ripple doesn't affect my circuits?
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When bit-banging I2C using 2 PIO lines do these lines still need to be pulled high? Obviously using a dedicated I2C bus the lines must be pulled high as the pins are open-drain outputs but PIO pins aren't open-drain.
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I'm trying to connect 32 I²C "root of trust"  devices.    I'm thinking about a good way that does that, I mean what kind of communication should I use? A digital multiplexer that selects a device? but based on what? switching on the VDD source? but that needs reinitialization of the device and that takes time.
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Manuals of several various electronic devices I came across recommend connecting their AC adaptor first into the device, then into mains. I always thought the reverse order is safer because I thought that connecting into mains can send a voltage spike into already connected device. Are power supplies (adaptors of laptops or other electronics) designed in a way that there is no risk of harm to their device when connecting? Are both connecting orders equally safe in these terms?
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I have some experience with I²C (TWI) as I used it before, but it seems I can't solve this particular problem. I intend to communicate two CPUs via I²C. One is always the master and the other is the slave. I'm defining the communication protocol myself, so it's somewhat flexible, but I intend it to be as efficient as possible (i.e. the fewer bytes, the better).  I want the slave to set NACK for certain values; for instance:  MASTER = START + sends SLAVE ADDRESS SLAVE = sets ACK MASTER = sends any one "byte" command SLAVE = sets ACK or NACK depending if "byte" was a valid command or not.   The last statement is the problem, because apparently I -as the slave- have to decide for ACK or NACK before receiving the one "byte" command; i.e., in response to TWSR = 0x60 (SLA+W received). The problem is, I don't know in advance if the command will be valid or not! Apparently setting or clearing the TWEA bit is only effective for the next byte to be received.  As much as I digged into the docs, I cannot find a way to respond with NACK "on the fly" because the ATMega sets the interrupt AFTER sending the ACK (or NACK). TWSR will be either 0x80 or 0x88, which means "byte received, ACK sent" and "byte received, NACK sent" respectively.  Aside from adding padding bytes or implementing a bit-banging I²C library, is there some way to solve this?  The master controller is an NXP LPC2148, while the slave controller is an ATMega1284P.  Thank you.
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I hope this question won't be closed as too subjective. I'd like to know best practice - how to make traces on universal PCB's with individual holes without traces (like the following image). My idea is to bend the ends of discrete components and use them to make traces to other components. Is this approach acceptable, or nasty? Although this is called "prototype" PCB, I'd like to use it for my simple final circuits (low frequency, low current applications), because I hope it will save time.
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On some PCB designs, specific traces are routed in curious ways. This probably has to do with high frequency design considerations and general signal behavior that I am not familiar with.  Let's take this PCB (somewhere from the web) as an example. It shows part of a PCIe card with SATA routing and DDR2 RAM:    I highlighted 4 areas that qualify as unusual trace layout (from my perspective).   What are those shapes supposed to achieve? How do designers come up with what pattern is required? Another example of wave shaped, antenna like routing. This is fairly rare. But obviously the designer deliberately avoided 45° traces. Why? Curves again and a single "pulse" within the trace. How can this have any significant effect?   So what are the use cases and benefits of this techniques?   I want to be able to take those into consideration when doing future PCB designs.
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I have a 6-layer board where the internal 4 planes are +15,GND,VCC,-15.  I was wondering if there was any advantage to doing a copper pour on the top and bottom layers?  I would probably leave them floating as I don't want to use micro-vias to say tie it to GND?    Is this actually a bad idea?  I.e. floating copper=antenna.  Would it be just as acceptable to have 4 layer board with the top layer having copper pour to VCC and the bottom having a pour to GND and keep the two internals as +-15?  Note that this is for a fairly low speed circuit which has some analog and digital parts.
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I have a circuit which has an input of voltage of the order of micro. I want to convert it into volt order. I am using an instrumentation amplifier AD620 with gain of 1000 to first convert it into milli order. And then I am using TL084cn as a comparator whose one input is the milli order voltage and the other is grounded. The +Vcc and -Vcc is 10 V. Also the frequency of operation is between 8-40 Hz. The question is that theoretically this is possible but before I implement it practically I would want to know whether I could face some issue for such sudden abrupt change in the order of the voltage.  Also, keep in mind please that I don't actually care about the shape of the signal cause in my project the information is in frequency and not in amplitude.