I want a synchronous D-flip flop with three input,reset,D and CLK,but i can't find it,only four or two inputs,and four inputs just D,CLK,Set and reset ,but find the asynchronous D-flip flop with three input on the Internet.  Can i do anything to let asynchronous D-flip flop become synchronous D-flip flop ? For example,change NAND by AND .  Someone told me : take the 4 input one and ignore the set, that is, hold it false and remove any following logic that no longer changes state as a result,but i don't know last sentence meaning and the method.
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I can't find the schematic of D flip-flop with synchronous reset , that is , D flip-flop with three inputs, D,CLK and reset ; and two outputs ,Q1 and Q2  I only found the schematic with "two"  inputs,D and CLK;or  "four"  inputs, D,CLK,reset and set,from the Internet.  Can anyone help me??please.......
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For 3 input XOR gate and XNOR gate, by solving the equations I got the result as in the picture.  So according to the solution the outputs of the 3 input XOR and XNOR gates are same. This solution holds good when number of inputs to the gates are odd.   For the case of even number of inputs XOR and XNOR are complement to each other.   With this assumption the answer to the circuit in the picture should be option A,B, and C. but the correct answer is D. I am confused as to how?   Thanks in advance for the help.
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I can think of several examples of functions such that twice application of the function is equivalent to no application of it.   Additive inverse Multiplicative inverse Fourier transform Complex conjugation Any group built up from $\mathbb{Z}_2$, applying (one of) the $\mathbb{Z}_2$ parts' operation.   "Idempotent" came to mind, but that's wrong. It means $f(f(x)) = f(x)$, not $f(f(x))=x$.  What is the word for this "flip-flop" property?
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I have an STM32 that toggles nine GPIO pins repeatedly (one clock pin and eight data pins to load an FPGA image using SelectMap). I am doing this using the standard library function GPIO_WriteBit that modifies one GPIO bit, and changing one pin at a time.  Unfortunately, this turns out to be quite slow. Is there a way I can make "raw GPIO toggles" very very fast? Is there a clock parameter I should change? Can I use some sort of FIFO, or interrupt-based method?  I have configured the GPIO pins as follows:    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;   (Note: The  (see page 133) states that the GPIO is capable of:  Fast toggle capable of changing every two clock cycles   But I cannot see how to activate this fast toggling.)
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From .   "A (bi-directional, deterministic) cellular automaton is a triplet $A = (S;N;\delta)$, where $S$ is an non-empty state set, $N$ is the neighborhood system, and $\delta$ is the local transition function (rule). This function deﬁnes the rule of calculating the cell’s state at $t +1$ time step, given the states of the neighborhood cells at previous time step $t$"  I haven't found other "bidirectional" CA via Google, so I wonder what does the term say about this automaton's properties. Does it mean that the state $t+1$ can be used to find out the state t?
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I have this function to read key press from a 4x3 key-board:  uint8_t GetKeyPressed() {   uint8_t r,c;    KEYPAD_PORT|= 0X0F;    for(c=0;c&lt;3;c++)   {      KEYPAD_DDR&amp;=~(0X7F);       KEYPAD_DDR|=(0X40&gt;&gt;c);      for(r=0;r&lt;4;r++)      {         if(!(KEYPAD_PIN &amp; (0X08&gt;&gt;r)))         {            return (r*3+c);         }      }   }  return 0XFF;//Indicate No key pressed }   Some macro, I missed:      #define KEYPAD A       #define KEYPAD_PORT PORT(KEYPAD)     #define KEYPAD_DDR   DDR(KEYPAD)     #define KEYPAD_PIN   PIN(KEYPAD)   But I don't understand this code, pretty well, because of those bit shifting operations.  Can anyone help me with this code?  Compiler : avr-gcc  Micro-controller : ATmega328
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I try to resolve a problem, how to implement a xor gate with nand's gate.  A xor B = A'B + AB'  So, this becomes :  A xor B = A'B + AB' + AA' + BB' = A(A' + B') + B(A' + B') = (A + B)(A' + B') =   (with De Morgan apllied on the second term)  = (A + B)(AB)' = ..... ?  In this point i am blocked. If someone can help me, please. Thank you.
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Is there any IC that interfaces any 3.3V Input/Output to 5V Output/Input? I need it primarily for an Arduino Due but if there any bidirectional IC that works like that it would be great.  Some people advised me to use the SN74AHC125 and CD4050 ICs, but I don't understand how they work or how to interface with them.
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So I'm trying to wire up a  just with NPN BJT transistors (I know there is a 74XX283 4-bit binary full adder, but I want to do it just with transistors if possible for my own learning).  The full adder I'm trying to build looks like the following with logic gate symbols:      I use a NAND, OR and AND gate to build the XOR gate:      Right now my current circuit looks like this:         &ndash; Schematic created using   Schematic notes:      All those 1k resistors you see going to ground are pull down resistors, so I get a more cleaner signal, but I'm not sure if they are required or optional or where and when exactly I need them.   But the circuit does not work as intended:  A B CIn | Sum COut ------------------ 0 0 0   | 0   0   (Both LEDs are clearly off) 0 0 1   | 1   0   (A clear one the LED glows; the other is off) 0 1 0   | 1/2 0   (The LED just glows like half; the other is off) 1 0 0   | 1/2 0   (The LED just glows like half; the other is off) 1 1 0   | 0   1/2 (The LED just glows like half; the other is off) 1 0 1   | 0   1/8 (The LED just barely glows; the other is off) 0 1 1   | 0   1/8 (The LED just barely glows; the other is off) 1 1 1   | 1   1   (Both LEDs only glow half)   The expected behaviour would be:  A B CIn | Sum COut ------------------ 0 0 0   | 0   0 0 0 1   | 1   0 0 1 0   | 1   0 1 0 0   | 1   0 1 1 0   | 0   1 1 0 1   | 0   1 0 1 1   | 0   1 1 1 1   | 1   1   I have tried to remove, change or add some pull down resistors on the gate outputs, but the above circuit is the best attempt I have right now. I have also changed out all components and the breadboard I use, just to make sure it isn't some component that is dead. I already have double/triple checked all resistors and connections, so that I don't just have a misplaced wire or wrong resistor.  I also tried to use a multimeter to find the error, but that just confused me more. But if I have to I can also check stuff with the multimeter if necessary.  So I'm at the end with my knowledge here how to fix my circuit design and get a clear on and off output?  I don't know if I use wrong resistor values, I don't use the transistors correctly or if my design is wrong from the start.
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Is the below a valid circuit implementation and are there any things to watch out for? It's a simplification of the larger circuit but the crux of it is that I need to sink current into two GPIO input pins. The pins are signified by the 1 and 0.  Also, would a diode on the pins be advisable?    Edit: Here's the non-simplified circuit. The question relates to the 3.3v part of it. In essence, the timer and decade counter sequentially pulse current, 'activating' the transistors one at a time. The keypad is a simple matrix keypad. What I'm wondering if I can do is to put a GPIO pin on the line between the keypad and ground. The intended effect is that, when a button on the keypad is pressed, 2 pins will change state - this signifies the row and column.  Note that some of the resistance and capacitance values are notional at the moment.
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I'm having trouble with part of a build I have to do. I've built this circuit: \$I = A\bullet(B + C + D + E + F)\$  The \$+\$ is OR, \$\bullet\$ is AND, and I'm using 2-input OR gates.  The output signal is for an alarm.  I need a latched output - I need to derive a simple logic circuit using 1 OR and 1 AND logic gate, that could be added to the alarm output signal.  It should latch the alarm output signal once the alarm has been triggered, and the latched condition should require a cycle of the master switch to reset the alarm.  I googled for answers but couldn't find any... e.g. A site I love for Digital Electronics and Circuit Theory is   If someone could tell me what I need to do, or point me in the right direction that'd be great.
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I am designing a hobby project that will run on a battery so I am trying to reduce power consumption. The SoC I am using has the ability to go into a deep sleep mode where it consumes very little power, and then can be interrupted by a falling edge on a pin.  I want to generate a high-low-high pulse when the state of a reed switch changes in either direction. I have been reading a lot and it seems that a one-shot monostable circuit can be built from a couple of transistors and an RC circuit to generate an output pulse when an edge is detected. I understand how that works. However, I can't figure out the best way to also pulse on the opposite edge.  One thought, was to just combine two one-shots that are configured to trigger on rising and falling edges respectively, and use the transistors at the output to pull the common pull-up low (kind of like a NOR gate).  Since I am a hobbyist, I am mostly using passive components. What is the "real" way of doing this in a low-power configuration using logic devices?  Edit: I figure I should mention something about the timing requirements. Normally the reed switch will be either open or closed for many seconds at minimum before changing states.  Edit: Here is an example of the circuit I was using for detecting only the falling edge:    And here is the ~20ms pulse it was producing for ~200ms button press simulating the reed switch (Channel 1 is Vbe for T1 and Channel 2 is measured at RST):
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I know that a NOT gate always inverts its input.  When the input is "ON" I can imagine the gate stopping the flow of current.  But how does the gate generates flow of current when the input is OFF?  Please could you explain how this happens as simply as possible, I'm new to electronics ;)
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Most of the interface devices have various flag bits (that can also raise interrupts if that functionality is provided) used to check the status of the device/operation.  Usually they are cleared by writing a '1' to said bit.  Just some questions regarding this ...   Why are they cleared by writing a 1? I mean if the flag is already set to 1 by the device, won't it make sense to clear it by writing a 0 to it? Lets say i have a 8 bit status register with bits distributed as (picked from datasheet of NRF24L01+)     If bit 5 (TX_DS) gets set (ie. turns to 1) and I want to clear it by writing 1 to it, what value do I write to the register.
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I'm trying to perform a bitwise NOT in SQL Server. I'd like to do something like this:  update foo set Sync = NOT @IsNew   Note: I started writing this and found out the answer to my own question before I finished. I still wanted to share with the community, since this piece of documentation was lacking on MSDN (until I added it to the Community Content there, too).
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This is supposed to be a simple NAND gate. I understand how the output is 1 if one of the inputs is zero but if both inputs are 1 then the base of Q1 is supposed to be zero. This is what I don't understand. I know that Q2 and Q3 will be in cut off so the base of Q1 is floating. If that is true, how is it zero then?When A and B are open does current flow through Q2  Q3 via R1 to turn on Q1?
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I am looking to build a circuit to control five different FET drivers individually. The input signal would be a single shot from a function generator, which should produce five output signals, with the same frequency and phase but the duty cycles need to be individually controllable. Basically, I am trying to replace five function generators (synchronized to the same clock) with one single function generator and a circuit board due to limited resources. The outputs need to have only two levels i.e pulse wave  EDIT: Olin's suggestion (using a MCU) or a FPGA seem to be the best options but any analog alternatives are much appreciated. Thanks :)