I have difficulties understanding what happens in MOS-FET-pinch-off: Take an N-MOSFET:  Near the source the gate-bulk voltage is high enough to form an inversion layer. So we have electrons as majorities in the inversion layer. As the channel potential increases towards the drain, there is less voltage difference to form an inversion layer. Ultimately, close to the drain the difference is insufficient to form an inversion-layer.  So we have a thin depleted p-layer or i-layer. I don't understand why this is still conducting.  To me this looks like an N(source), N(channel), P(pinchoff-area), N(drain) structure. I would expect that to isolate or at least require an Uf between drain and source to conduct, which is not the case.  What am I getting wrong ?     I would be interested to see a band-model-diagram from source to drain for a MOSFET in pinch-off, but I have never found any, neither in a book nor on the web.
123742
Here is what I have understood. Please correct me if I'm wrong.  The depth of induced channel depends on the voltage V. Since the voltage across the gate and  the path along the channel decreases from Vgs at the source to drain end to drain end, the channel is not uniform an is tapered. If the applied voltage Vds is increased to some value which causes the voltage between gate and drain end to be lesser than the threshold voltage, the channel is said to be pinched off.  If the channel is pinched off, how does the drain current flow? It's given in the book that the MOSFET enters saturation region and will have a constant value of drain current. But I don't understand how does the current flow when the channel no longer exists at the drain end.
60196
I have recently been looking at the datasheets for the  IC in order to see if it was suitable for my project, and have come across the following logic diagram which strikes me as a little bit odd:         &ndash; Schematic created using   For each of the inputs Yn, there are two NOT gates after the triple-input NAND gate; I don't understand why this is necessary as simple boolean logic tells us:  $$\overline{\overline{A}}\equiv A\qquad \forall A \in \{\text{TRUE}, \text{FALSE}\}$$  Therefore I am assuming there is some electronic based reason why there are two inverters before the output? I have heard not gates called Inverting buffers before, and these supposedly isolate the circuit before and after, however, I cannot claim to understand the use of this so I'd appreciate any enlightenment!
72807
At the risk of being blasted for cross-posting, I am posting this question again here in the Physics department. It is a duplicate of  in the EE forum. However, I would like to get some answers from more of a Physicist perspective and less of an Engineer. I don't like the fact I have to post it twice either, but I don't know how else to get the right audience to answer it here on StackExchange.  We use them every day and those in the know fully understand the functional characteristics of BJT transistors. There are documents and links galore explaining the operational math. There are even tons of nice videos that explain current theories of how they physically work. ( Most of the latter given by folks that speak "Tele-marketer English" for some reason. )  However, I have to admit, even after 40+ years, a lot of it I have to accept at face value, since the descriptions of how the collector junction fits into the equation is always a bit hand-wavy.   Anyhow, that aside, there is one facet I really just don't get. It seems to defy the laws of physics, Kirchhoff's Laws et.al.  I'm talking about your standard saturated common emitter circuit.  It is known, and we accept, that when saturated, the collector voltage will be less than the base voltage. We obviously use that to our advantage in circuits and chose parts to give us as low a Vce-Sat as possible for a particular load current.     All fine and dandy, till you look at the quintessential mode of a typical NPN transistor...    How the heck can the collector be a lower voltage than the base in that sandwich?   Even if you add in some back-EMF type voltage in there to account for it, the collector current would be going the wrong way through the base-collector junction..    The EE group have some answers that present theories that, to the most part, explain the phenomenon, but some of that theory seems rather conflicting.
111942
I have this formula for the current based on conductivity but I cannot see the influence of the gate voltage. What does it change ? Is it the value of the conductivity that must be shifted as the potential barrier of the channel is shifted ?  Thanks
25751
Another form of the question is: will joining two diodes with wires (pn-np) make a transistor-equivalent?  I read that they are not equivalent, but why?
77221
This image from wikipedia, explains that there occurs a potential drop across a , and an electric field confined to the depletion region.  I already know the reason for the existence of this drop and the calculation of the difference but I have two questions regarding this drop.    1) If the  regions are externally connected using a perfectly conducting wire, why will not any current flow? Connecting the two regions should equalize their potentials (since wire is a resistance less) conductor, and therefore the gradient at the junction is destroyed resulting in a  which is obviously against conservation of energy as the semiconductor has non-zero resistivity. Where will extra potential drops will be created so that Kirchoff's voltage rule holds without any current and the built-in potential difference $V_o$ of the juction persists?    2) (probably naive) If an external Bias is applied, of say $|V|&lt;|V_o|$, then the pn potential difference across the junction will just reduce by that amount ($|V|$). Assuming that the external voltage source is ideal without any resistance, what will be the potential drops which would sum to zero in this case? Will drop due to the resistance of semiconductor play a par in it? If yes, then there cannot be any ideal resistance-less semiconductor junction, can there?
102608
So for some MOSFETs, specially with Power MOSFETs, the body diode is a flyback diode that (as far as aI can tell) can be conveniently added to the MOSFET's bulk as there already PN junctions (correct me if I'm wrong).  I've looked at the datasheet of a Power P-MOSFET and it has parameters like "Internal Source Inductance" and "Internal Drain Inductance". So, is the build up of reverse voltage on the source and drain sides, when said MOSFET is suddenly turned off, a behavior intrinsic to (at least some) MOSFETs? Or are these from the rest of the circuit, say inductive loads?
87289
I am currently dealing with current mirrors and came across the circuit shown below, a High-Swing Cascode Current Mirror. I read that this implementation, as the name suggests, has the advantage of a high voltage headroom, since the minimum potential at the drain terminal of M4 is: $$ V_{D4\_min}=V_{DS4}+V_{DS2}=(V_{GS4}-V_{TH})+(V_{GS2}-V_{TH}) $$ So the drain potential at M4 only needs to be twice the overdrive voltage, in case of same transistor dimensions, in order to hold M2 and M4 in saturation. But cannot this be said for many other cascode current mirrors, since that behaviour simply occurs by "stacking" together two transistors (M2 and M4)? Additionally, why is there a connection from the gate of M1 to the drain of M3? I have a hard time understanding whats going on in this circuit, help is greatly appreciated.    EDIT: A bias voltage source is setting the potential at the gate of M3/4. Sorry its not shown in the circuit.  EDIT 2: I just read that the mentioned bias voltage is implemented by a MOSFET in diode configuration, . For further discussion lets call it M5.
77283
I know this question sounds silly, as if there was a potential difference a current would be created when the terminals are connected together and this would mean energy has come from somewhere.  The reason I ask this though is that from my understanding of the depletion region and built in potential of a diode it seems like if you connected a voltmeter across the whole diode it would show the value of the built in potential.  This is explained in the image below:    At first, electrons flow from the n type to the p type because there are a higher concentration in the n type, and holes do vise versa. This is called the diffusion current. The first electrons and holes to cross the pn boundary are the ones which are closest to it; these carriers recombine when they meet each other and are then no longer a carrier. This means there is a depletion region of no carriers near the pn boundary. because electrons have left the n type material, and holes have left the p type material, there is a surplus of positive and negative charge on the n and p side of the pn boundary respectively. This causes an electric field that opposes the diffusion current, and so no more electrons or holes cross the boundary and combine. In short, only the electrons and holes near the boundary combine, because after they have done that an electric field is formed that prevents any more carriers from crossing. The current due to this electric field is called drift current, and when in equilibrium this will equal the diffusion current. Because there is an electric field at the boundary (pointing from the positive charge to the negative charge) there is an associated voltage. This is called the built in potential.  If you sample the electric field at each point along the diode from left to right, you would start with 0 in the p region because there are an equal number of protons and electrons. As you approach the depletion region you would see a small electric field pointing back towards the p region, caused by acceptor impurities which now have an extra electron (due to recombination) and therefore now have a net negative charge. This electric field would increase in strength as you get closer to the boundary, and then die away as you get further away.  This electric field means there is a voltage, as shown in graph (d). The p side is at an arbitrary potential, and the n side is at a potential higher than this because there is an electric field between them. This means there is a potential difference across the depletion region; this is known as the built-in potential.  But why when I connect a volt-meter across the whole diode will I not see this built in potential?
83189
I have n mosfet gate connected to  logic and Id is about 100mA. Both 4043 and mosfet has +5v. I have plan to use  mosfet  Questions are: How large gate resistor i need between 4043 and mosfet? Logic output is sometimes put on rapidly. How fast? Motherboard hdd led controls that. Do i need to place pull down resistor from logic to -0v, between 4043 and mosfet?
1533
I faced lots of circuits that has transistors connected as diodes (gate connected to the drain). I know some of these circuits employ such transistor for safety reason but I couldn't figure out the reasons of others.  My question: Is there any reason behind connecting the transistors as diodes other than the one I mentioned? Some of my colleagues suggest that they may be used to realize high resistance but I think connecting the transistor in such configuration (\$V_{g} = V_{d}\$) will force the transistor to work in saturation region, not in linear region. Am I right?
121975
Note that this is a theoretical question - there is no schematic I can show. I will show some schematic, but it will be a very simplified version of an actual circuit, only for illustration purposes.  Assume I have a voltage converter that takes as an input my main voltage (from a power supply) and outputs a certain voltage, for example 1.8V. It would look something like this:         &ndash; Schematic created using   When connecting my circuit to the P.S, I notice it draws too much current (the P.S shows that).  Since I have multiple voltage converters in my circuit (not shown here), I check resistance between each output of each converter to ground. I see that the resistance between 1.8V to ground is almost 0 Ohms. Now I know the fault is either in the voltage converter or one (or more) of the other components drawing power from that 1.8V.  I desolder the resistor shown in the image to disconnect the converter from the other components and see that the converter is fine, but checking resistance from the point connected to all those components still shows 0 Ohms.  My question is - how would you check which component is the faulty one, without desoldering each suspicious component? As you can see in the image, the 1.8V supply is connected directly to the components, without a resistor/bead.  For the sake of this question, assume I have access to whatever equipment needed (no matter how pricey). I wouldn't want solutions to be limited due to availability of equipment.  Thank you!
13740
For those of you that uses Advanced Design System (ADS), from this circuit:   Fundamental Frequency for transient simulation tool is set to 1GHz.  Yet, I'm getting this output:   Main question:  Since this is Common Drain, VOUT should at most have the same amplitude as VIN. Probably even negative shift, since I didn't change the voltage threshold (I haven't got to tweaking parameters yet). So what's up with the positive DC bias?? Why is the amplification significantly less than unity?  Other questions:  1.) Also, what's that Transient Response at the very first cycle of VOUT? Why would a semiconductor have a Transient Response? Is it because of the "inductance" on the drain and source of a MOSFET?  2.) Lastly, why is it that this simulation does not work on very low frequencies? I first started with 1Hz scale for everything (just change all units from 1GHz below to 1Hz). The M1 just acted like a 1kOhm constant resistor.  UPDATE:  Because of recent response, I bothered to simulate this in the 1kHz scale (replaced all units from GHz in the pics to kHz, did the same with Fundamental Frequency) -- really should've done that in the first place (stupid me). This is the output:    Even here, the DC bias is nearly the same and the amplification is much, much less. It also lags by 90°. Why?  I'm starting to think it's either just using the wrong component or there was a set of parameters to fill-in for this component to get this to work.  UPDATE:  the continuation of this discussion:
87509
I've tried really hard to understand the basic operational principle of a transistor. I've referred to many books and been to forums but have never got a convincing answer.  Here are the things I want to understand:   A transistor is similar to a reverse biased diode unless a voltage is applied to the Base.  Since the Emitter-Base junction is forward-biased, there will be conduction of - say - electrons (npn). What happens then? Is it true that these electrons from the Base break the barrier of the Collector-Base junction and then the combined current passes to the Emitter? (IB + IC = IE)  And why is that we are getting more current? Where is amplification? It can't be like creating something out of nothing. I know I'm missing some crucial point here. Can somebody explain me clearly in simple terms?  It has been a week I'm tryin to understand this. :(
33885
I'm a newbie in electronics and Trying to understand and build this circuit. would somebody tell me the rule of R1 &amp; C2 in this circuit and their magnitude effect on the controlling of process.why didnt feedback start just after the output of opamp?How could i find the transfer function between the voltage output of Hall effect sensor and the voltage output of MOSFET drain?  The schematic is the circuit of a magnetic levitating tool at:    Thanks so much
2622
Not-gate, if get a 0(Off) input, it gives an 1 (On) output. And if get a 1 (On) input, gives-back a 0(Off) output.  Now, if-I could bring the output back to the input of the not-gate, then what will happen? If the gate is getting a 1 input, it is giving a 0- output, and then if it is getting a 0 input, it is giving an 1 output.  The situation sounds-like a physical-model of a "self-contradiction" (self- false)  (like when fever-attacked kid-Bertrand Russel waiting to be april-fooled by his brother, taking preparation against all possible tricks,  Bertrand Russel's brother made Bertrand an april-fool by doing "no-april-fool" at all; and if Bertrand's brother uses any april-fool trick, Bertrand will Not be april-fooled, and if Bertrand's brother use no april fool that means Bertrand hasbeen april-fooled by-his brother).  Now, what will-be happen in case of the real hardware called a NOT gate?  I ASSUME the possibilities;   the gate will always remain as 0 (off)-output . the gate will always remain as 1(on)-output . The gate will be "PULSATING"; once it will 1 output; at the next-moment, after receiving that 1(on)-signal it will give-out a Zero (off) signal, and the cycle will run on and on. The frequency of this oscillation will depend on physical-characteristics of circuit component. the circuit will be get-damaged ( due to some anomalous current, overheating, etc) and soon permanently stop working.   Will something happen within-these assumptions?   PS. I'm thinking about this-problem from my schooldays, but since yet I do-not know, how to assemble a not-gate in a circuit, from-where they could be bought, etc; I yet could-not test it experimentally.
101729
Does anyone know if a finite number of parallel-series impedance has a general solution?  I am trying to model a network flow problem that can be described in electrical terms and represented as a finite discrete transmission line with arbitrary impedance.  While it is not difficult to write the equations down for a small number of terms, I'm curious if there are some general solutions or insights into the problem.  It looks like  ----Z1---+----Z3---+----Z5---+---...---+          |         |         |         |          Z2        Z4        Z6        ZN          |         |         |         | ---------+---------+---------+---...---+   All the Z's are, in general, different.  I'll need to know the "current" and/or "voltage" at every branch. In this case the bottom is grounded.  What would be cool is to be able to know the voltage and/or current in terms of i, the ith position (the top +).  Any ideas?